Intermediate Bus Voltages in GPIF™ II Master Mode - KBA90278

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    Question: If DR_DATA is used in a state following a DR_ADDR state when the address and data buses are multiplexed in the GPIF™ II master mode, there are intermediate voltages on the address and data bus. Why does this occur and is there a workaround for this?



    The GPIF II hardware updates the address value towards the end of the state’s cycle whereas the data is updated towards its beginning. Therefore, when DR_ADDR is followed by DR_DATA, as shown in Figure (a), the address/data bus might show intermediate voltages. To prevent this, use a wait state, as shown in Figure (b).

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