Version: **
Question: Can the pipeline condition create a difference in access cycles (from fetch to execution) even when accessing the same register?
Answer: Yes. Even when accessing the same register, the access cycle differs depending on the pipeline condition in the ARM®.
Any consecutive instructions having load/store phases can pipeline. For example, two consecutive read instructions using CY_GET_REG8(address) can pipeline. To find this, go to the Disassembly window of PSoC® Creator™ in debug mode and check the assembly instructions. If there are ldrb and strb instructions for each of these codes, they can pipeline.
According the Cortex-M3 Technical Reference Manual, load (ldrb) and store (strb) instructions take two cycles each. However, neighboring load and store single instructions can pipeline their address and data phases. This enables these instructions to complete in a single execution cycle.
Here is an example:
(Case1)
NOP
NOP
NOP
Write Data to ADC Control Register
NOP
NOP
NOP
NOP
(Case2)
Write Data to a register
Write Data to a register
Write Data to ADC Control Register
NOP
NOP
Writing data to the ADC control register takes a maximum of six cycles. So, Case 1 can take a maximum of six cycles but Case 2 can pipeline stages so the number of cycles will be fewer.
You can refer to the Cortex-M3 Technical Reference Manual to find the number of cycles taken by each instruction and the pipeline condition.
