K/K# Clocks Routing for QDR®II/II+/DDRII/DDRII+ SRAMs – KBA89248

Version 2

    Version: **


    Translation - Japanese: QDR®II/II+/DDRII/DDRII+ SRAMsのK/K# Clocksクロックのルーティング – KBA89248 - Community Translated (JA)


    Question: Should you treat the K/K# clocks as single-ended or as differential signals in PCB routing?



    K/K# clocks should be treated as single-ended signals and have to be routed as independent traces that are decoupled from one another. However, to minimize the timing issues and skew between these clocks at the receiver side, the lengths of these two traces on PCB have to be the same.

    The clocks are not true differential signals; they are pseudo-differential clocks. Both clocks are single-ended signals, 180 degrees out of phase with each other. They should be terminated like other signals with pull-up resistor to VTT.