Question: Why does jitter appear at the clock output of a high-frequency clock? How can it be avoided?
Consider the following schematic:
Figure 1. Clock Component Used in the Top Design
In Figure 1, the clock component is configured for 1 MHz and derived from the internal main oscillator (IMO), such as the 24-MHz IMO.
The master clock used in the design is derived from PLL_OUT. Figure 2 shows the clock configuration tree that is used in the design.
Figure 2. Clock Configuration Tree
So, in this project, Master Clock is derived from PLL_OUT, while the clock source Clock_1 is based on the IMO. The PLL is uncorrelated to the IMO-based 1-MHz clock. This asynchronicity makes it indeterminate on the PLL clock cycle that will re-sync the IMO-based divided clock. This causes jitter on the clock output.
To eliminate this jitter, do one of the following: