Question: What type of jitter is specified by tKC Var (clock phase jitter) in DDR/QDR™ Sync SRAM?
The QDR Consortium officially specifies input-clock phase jitter as cycle-to-cycle jitter, which measures the change in clock period measurement between any two adjacent clock cycles.
Mathematically, the cycle-to-cycle jitter can be represented as follows:
Tcycle (n) – Tcycle (n+1)
where Tcycle (n) and Tcycle (n+1) are any two adjacent cycles measured on controlled edges.
Consider the following figure, which shows the various cycles of the input clock K:
Suppose the QDR/DDR Sync SRAM is operated at 250 MHz. Then the K clock period ideally should be 4 ns.
- For zero jitter, Tcycle (n) = Tcycle (n+1) = 4 ns.
- If Tcycle (n) = 4 ns and Tcycle (n+1) = 3.9 ns, then the jitter would be (4 ns-3.9 ns) = 0.1 ns. This calculated jitter should be less than or equal to the tKC Var parameter specified in the datasheet for proper operation.