Question: Should the clocks in QDR/DDR Sync SRAMs be routed as single-ended or differential?
The clocks in QDR/DDR Sync SRAMs should be routed as single-ended. The echo clocks (CQ and /CQ), which are used to simplify data capture on high-speed systems, are not truly differential signals. They are single-ended signals that are 180 degrees out of phase. So, you need to route these signals as single-ended, but ensure that both signals have minimum skew with respect to each other.
The same is true for the input clocks (K and /K). Please note that there is no differential receiver in the SRAM. The memory uses the rising edges of K and /K to latch input signals. Both clocks are single-ended signals. Although they are not truly differential, it is best to keep K and /K 180 degrees out of phase with respect to one another.
Please note that although there is no special requirement to route CQ and /CQ and K and /K close to each other, the trace characteristic length should match so that there is no skew between them. Since these are pseudo-differential clocks, the rising edge of one clock and the falling edge of the other clock should match.