General-Purpose Memory Controller (GPMC) Configuration for Interfacing the TI Processor (AM335x) with Dual-Port Memories – KBA91141

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    Question: What is the GPMC configuration for interfacing the TI processor (AM335x) with Dual-Port memories?

     

    Answer:

    The TI processor (AM335x) has GPMC configuration registers. Based on the programmed configuration bit fields stored in the GPMC registers, the GPMC is able to generate all control signals for the Dual-Port memories. In the TI document, there are memory-mapped registers for GPMC.

    GPMC Configuration Setting:

    GPMC_CONFIG1_i: Sets the control parameter per chip select

    GPMC_CONFIG2_i: Chip select signal timing parameter configuration

    GPMC_CONFIG3_i: Address valid signal timing parameter configuration

    GPMC_CONFIG4_i: /WE and /OE signals timing parameter configuration

    GPMC_CONFIG5_i: Read access time and cycle time timing parameter configuration

    GPMC_CONFIG6_i: Write access time, write data on ADmux Bus, Cycle2Cycle, and Bus Turn Around parameters configuration

    GPMC_CONFIG7_i: Chip Select address mapping configuration

    Note: i in GPMC_CONFIGx_i stands for the GPMC chip-select i where i = 0 to 6 and x stands for GPMC memory mapped registers.

    Each control signal is controlled independently for each chip select. The internal functional clock of the GPMC (GPMC_FCLK) is used as a time reference to specify the following:

    •   Read- and write-access duration
    •   Most GPMC external interface control-signal assertion and deassertion times
    •   Data-capture time during read access
    •   Duration of idle time between accesses, when required

    Table 1 shows a few examples of the GPMC configuration registers setting.

    Table 1. GPMC Configuration Register Settings: GPMC_CONFIG1_i—Sets Signal Control Parameters per Chip Select

                                                                                                                                                                 
        Bit    Field    Description
        GPMC_CONFIG1_0 Register - Sets signal control parameters per chip select
        30    READMULTIPLE    Selects the read single or multiple access    

         0h = single access

       

         1h = multiple access (burst if synchronous, page if asynchronous)

      
        29    READTYPE    Selects the read mode operation    

         0h = Read Asynchronous

       

         1h = Read Synchronous

      
        28    WRITEMULTIPLE    Selects the write single or multiple access    

         0h = Single access

       

         1h = Multiple access (burst if synchronous, considered as single if asynchronous)

      
        27    WRITETYPE    Selects the write mode operation    

         0h = Write Asynchronous

       

         1h = Write Synchronous

      
        13-12    DEVICESIZE    Selects the device size attached    

         0h = 8 bit

       

         1h = 16 bit

       

         2h = Reserved

       

         3h = Reserved

      
        11-10    DEVICETYPE    Selects the attached device type    

         0h = NOR Flash like, asynchronous and synchronous devices

       

         1h = Reserved

       

         2h = NAND Flash like devices, stream mode

       

         3h = Reserved

      
        9-8    MUXADDDATA    Enables the Address and data multiplexed protocol    

         0h = Non-multiplexed attached device

       

         1h = AAD-multiplexed protocol device

       

         2h = Address and data multiplexed attached device

       

         3h = Reserved

      

    Table 2. GPMC Configuration Register Settings: GPMC_CONFIG2_i —Chip Select Signal Timing Parameter Configuration

                                                                                                           
        Bit    Field    Description
        GPMC_CONFIG2_0 Register - Chip-select signal timing parameter configuration
        20-16    CSWROFFTIME    /CS de-assertion time from start cycle time for write accesses    

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 31 GPMC_FCLK cycles

      
        12-8    CSRDOFFTIME    /CS de-assertion time from start cycle time for read accesses    

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 31 GPMC_FCLK cycles0h = Read Asynchronous

       

         1h = Read Synchronous

      
        7    CSEXTRADELAY   

         /CS Add Extra Half GPMC.FCLK c

       

         0h = CS i Timing control signal is not delayed

       

         1h = CS i Timing control signal is delayed of half GPMC_FCLK clock cycle

      
        3-0    CSONTIME    /CS assertion time from start cycle time    

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 15 GPMC_FCLK cycles

      


    Table 3. GPMC Configuration Register Settings: GPMC_CONFIG4_i—/WE and /OE Signals Timing Parameter Configuration
     

                                                                                                                                               
        Bit    Field    Description
        GPMC_CONFIG4_0 Register - WE# and OE# signals timing parameter configuration
        28-24    WEOFFTIME   

         WE# de-assertion time from start cycle time

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 31 GPMC_FCLK cycles

      
        23    WEEXTRADELAY   

         WE# Add Extra Half GPMC.FCLK cycle

       

         0h = WE (active low) Timing control signal is not delayed

       

         1h = WE (active low) Timing control signal is delayed of half GPMC_FCLK clock cycle

       

          

      
        19-16    WEONTIME   

         WE# assertion time from start cycle time

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         Fh = 15 GPMC_FCLK cycles

      
        12-8    OEOFFTIME   

         OE# de-assertion time from start cycle time

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         7h = 31 GPMC_FCLK cycles

      
        7    OEEXTRADELAY   

         OE# Add Extra Half GPMC.FCLK cycle

       

         0h = OE (active low) Timing control signal is not delayed

       

         1h = OE (active low) Timing control signal is delayed of half

       

         GPMC_FCLK clock cycle

      
        3-0    OEONTIME   

         OE# assertion time from start cycle time

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         Fh = 15 GPMC_FCLK cycles

      

    Table 4. GPMC Configuration Register Settings: GPMC_CONFIG5_i—RdAccessTime and CycleTime Timing Parameters Configuration

                                                                                                     
        Bit    Field    Description
        GPMC_CONFIG5_0 Register - RdAccessTime and CycleTime timing parameters configuration
        20-16    RDACCESSTIME   

         Delay between start cycle time and first data valid

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 31 GPMC_FCLK cycles

      
        12-8    WRCYCLETIME   

         Total write cycle time

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 31 GPMC_FCLK cycles

       

          

      
        4-0    RDCYCLETIME   

         Total read cycle time

       

         0h = 0 GPMC_FCLK cycle

       

         1h = 1 GPMC_FCLK cycle

       

         1Fh = 31 GPMC_FCLK cycles

       

          

      

    For interfacing the TI Processor (AM335x) with Dual-Port memories, refer to KBA91121.

    Note: The following configuration settings are not shown in Table 4.

    •   GPMC_CONFIG3_i: Address valid signal timing parameter configuration
    •   GPMC_CONFIG6_i: Write Access Time, Write Data on ADmux Bus, Cycle2Cycle, and Bus Turn Around parameters configuration
    •   GPMC_CONFIG7_i: Chip Select address mapping configuration