CPU Code Execution and Writing to Flash Memory of PSoC® 3/4/5LP Devices - KBA90912

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    Translation - Japanese: PSoC® 3/4/5LP デバイス CPU のコード実行とフラッシュメモリへの書込み - KBA90912 - Community Translated (JA)


    Question: Will the CPU execution be halted during a flash memory write in PSoC 3/4/5LP devices?



    In PSoC 3/4/5LP devices, writing into the flash memory is blocking. PSoC 3/4/5LP devices have an internal hardware block named System Performance Controller (SPC), which performs erase and program operations on the nonvolatile memory. CPU code execution from the flash memory will be halted until SPC completes writing the data to the flash memory.

    In PSoC 3/5LP devices, the flash memory can be read either by the cache controller or the SPC; however, flash memory write can be performed only by the SPC. SPC and cache controller cannot simultaneously access the flash memory. If the cache controller tries to access the flash memory at the same time as the SPC, then the cache controller must wait until the SPC completes its flash memory access operation. The CPU, which accesses the flash memory through the cache controller, is therefore stalled in this circumstance.

    The CyWriteRowFull(), CyWriteRowData(), and CyWriteRowConfig() APIs write to the flash memory via the SPC. If a CPU code fetch has to be done from the flash memory due to a cache miss condition, then the cache controller will have to wait until the SPC completes the flash memory write operation. Thus the CPU code execution from the flash memory will be halted until the flash memory write is complete.

    PSoC 4 devices do not have cache memory. However, writing to the flash memory using the CySysFlashWriteRow() API is a blocking instruction and therefore CPU execution from the flash memory will be halted while a flash memory write is taking place. CPU execution will resume after the flash memory write operation.

    For PSoC 4 and PSoC 5LP devices, CPU can execute code from the SRAM memory while the flash write operation is underway.