Can Cypress SPI FLASH memory detect the correct bus SPI mode? KBA203367
It is important to note that neither the input data nor the output data will be latched if CS# is de-asserted inactive high.
The CS# must be asserted active low before the input data can be latched.
When CS# is asserted active low and SCLK is 1, mode-3 is detected;
When CS# is asserted active low and SCLK is 0, mode-0 is detected.
Input data and output data will be properly latched in mode-0 and mode-3.
The difference between mode-0 and mode-3 is the clock polarity when the bus master is in standby mode and not transferring any data (output).
Mode-0 and mode-3 latches input data on the rising edge of the SCLK;
Mode-1 and mode-2 latches input data on the falling edge of the SCLK.
Therefore, Cypress SPI Flash memory products latches input data on the rising edge of the SCLK, and latches output data on the rising edge of the SCLK (mode-0 or mode-3).