Connecting 2x8-bit Parallel NOR Flash Devices to MCU – KBA203626

Version: *A

 

Question:

Why can't I program/erase a Flash device?

 

Answer:

How do I connect 2x8-bit parallel NOR flash devices to the MCU?

 

For an 8-bit data bus connected to a single x8 flash device, denoted as 1x8 for one parallel NOR flash with eight data lines, the system address line A0 connects to the flash address line A0 on a flash device with eight data lines; the system address line A1 connects to flash address line A1, and so on. This connection defines a byte-addressable address space.

 

However, for a 16-bit data bus connected to two x8 flash devices, denoted as 2x8 for two parallel NOR flash with 16 data lines and flash address lines connected in parallel, system address lines need to be shifted to select (2B) words from the flash devices. If the system address line A0 selects bytes, then this system address line should not be connected to a flash address line.

 

Because the first system address line that selects a word is system address line A1, this should be connected to both flash address lines A0; system address line A2 should connect to both flash address lines A1; and so on. This connection defines a word-addressable address space.

 

The 2x8 case when using two dual-mode (x8/x16) Flash devices in byte mode is similar, except for the labeling of the address lines on this type of flash device. In this case, system address line A1 connects to flash address line A-1; system address line A2 connects to flash address line A0; and so on. As before, this connection defines a word-addressable address space.

 

Reading the programmed data from the flash device with a 2x8 configuration requires no special handling. However, writing flash commands and reading flash command response do require special handling by the system. This is because commands must be written in parallel to each 1x8 flash device, and command response must be read in parallel from each 1x8 flash device. In other words, flash command cycles must be duplicated within the 2B word that is sent to a word address, with one copy of the command cycle data in the low byte and one copy of the command cycle data in the high byte.

 

Similarly, the two flash devices transmit independent command responses in the low and high bytes. Status reads, in particular, require special logic to account for the fact that status in the two devices may not be synchronized. That is, if both flash devices receive a sector erase command at the same time, each device may be busy for a different period of time, so one device will become ready before the other.