What is the use of the Output Enable option in a digital output pin component of PSoC® 4?
In PSoC 4 devices, a GPIO pin configured as a digital output has a control signal called Output Enable (OE), in addition to the data signal. Output Enable can be controlled from firmware or by the hardware signals routed through Digital System Interconnect (DSI). The OE signal of a pin can enable or disable the output driver. When OE is logic high, the pin output is controlled according to the drive mode and the logic state of the source signal that controls the output. This source is the value of the port data register (PRTx_DR[y] – bit ‘y’ corresponds to pin ‘y’ of port ‘x’) in case of firmware-controlled I/O. When OE is logic low, the output driver is disabled and the pin is placed in HiZ. An example project that demonstrates how to control the OE signal of a pin is given in the “GPIO Tips and Tricks” section in AN86439 – PSoC 4 – Using GPIO Pins. The different ways of controlling OE and the corresponding component configuration in PSoC Creator are explained in the following sections.
Case 1: Controlling OE from Hardware
The “Output enable” setting should be selected in the Digital Output Pin component, as shown in Figure 1. A terminal to connect a hardware signal appears in the schematic symbol when Output enable is selected. Now a signal output from components can be routed to the terminal. The right side of Figure 1 shows that the output from a UDB-based control register component is connected to the OE terminal. The output from this component is routed through DSI by PSoC Creator in the background. In this case, the “HW connection” can be either selected or not selected. If the HW connection is selected, then another terminal appears to connect a hardware signal to control the data output. If the HW connection is not selected, the data output can be controlled by PRTx_DR register writes.
Which peripherals can control OE?
The peripherals that can control OE are TCPWM and UDB, which are the only peripherals that have routes to port pins through DSI and further through Port Adapter (PA). Other peripherals such as SCB, which have a dedicated route to pins not through DSI but through HSIOM, cannot control OE. Refer to the “Pin Routing” section in AN86439 – PSoC 4 – Using GPIO Pins to learn more about this. Note that PSoC Creator automatically manages the routing for you.
PSoC 4000 is a cost-optimized, entry-level device that does not have DSI and PA and hence does not support OE control. Also, Port 4 and higher ports in other PSoC 4 devices do not have PA and hence do not support OE control.
Figure 1 - Component Setting for Controlling OE from Hardware
Case 2: Controlling OE from Firmware
The “HW connection” setting should be selected and the “Output enable” setting should be unselected in the Digital Output Pin component, as shown in Figure 2. Now the schematic symbol of the pin has a terminal to connect a hardware signal to control the data output but does not have a terminal to control OE. The right side of Figure 2 shows that the output from a UDB-based PWM component is connected to the terminal to control the data output. Now, the OE can be controlled from firmware by writing into the PRTx_DR register. Writing “1” asserts OE and writing “0” deasserts OE. PSoC Creator configures the DR value to be “1” by default (Initial drive state is High (1) and cannot be changed) so that the data output is enabled at power-up.
Figure 2 - Component Setting for Controlling OE from Firmware
When OE cannot be controlled from firmware?
Note that OE cannot be controlled from firmware when HW connection is not selected (that is, both HW connection and Output enable are not selected in which case PRTx_DR is used to control the Data output) and when the HW connection is selected but the pin is connected to a hardware block with a dedicated route to the pin (in other words, the signal that controls the Data output is not routed through DSI). Pins of the PSoC 4 devices are shared for dedicated connections to different peripherals. For example, P3 in CY8C4245AXI-483 device has a dedicated route to “SCL” signal of SCB1. To know the functions possible at each pin, see the “Pinouts” section in the respective device datasheet.