Clearing UDB FIFOs - KBA91826

Version: **

 

Question:

How can the FIFOs in UDB be cleared? 

 

Answer:

Each UDB has an Auxiliary Control register (AUX_CTL). This register is used for multiple functions in the UDB, which could belong to different Components. Modifying the Aux Control register must be done with interrupts disabled. Critical regions are used to protect the update of Aux Control.

                                                                                            
Auxiliary Control Register
76543210
  CNT
    START
INT
    EN
FIFO1
    LVL
FIFO0
    LVL
FIFO1
    CLR
FIFO0
    CLR

Aux Control configuration bits (All bits initialized to 0) 

                                                            
[5] CNT STARTSW enable for the Count7 function
[4] INT ENInterrupt enable for the Status register in Interrupt mode
[3], [2] FIFO LVLFull/Empty or Half Full/Empty
[1], [0] FIFO CLRFIFO Clear

Use the following sample Code snippet to clear the FIFO:  

#define MyInstance_AUX_CTL_REG (* (reg8 *) MyInstance__DP_AUX_CTL_REG) 
uint8 preserveIntr;
/* Clear FIFO1 inside of a Critical Region */
preserveIntr = CyEnterCriticalSection(); 
MyInstance_AUX_CTL_REG |= 0x2; 
MyInstance_AUC_CTL_REG &= ~0x2; 

CyExitCriticalSection(preserveIntr);