Pin Mapping Differences Between EZ-BLE PRoC Evaluation Board (CYBLE-212019- EVAL) and BLE Pioneer Kit (CY8CKIT-042-BLE) - KBA210896

Version 3

    Version: *A

     

    Question: What are the differences between the pins exposed on J1 and J2 headers of the EZ-BLE™ PRoC™ Evaluation Board (CYBLE-212019-EVAL) and the pins expected by the J10 and J11 headers on the BLE Pioneer Kit (CY8CKIT-042-BLE)?

     

    Answer: Yes, there are differences between the pins exposed. The EZ-BLE PRoC Evaluation Board quick start guide explains how to use the board with the BLE Pioneer Kit and the differences in pin mapping. The details are also explained here.

    Figure 1 shows the J10 and J11 headers on the BLE Pioneer Kit.

     

    Figure 1. J10 and J11 Headers on BLE Pioneer Kit

    The EZ-BLE PROC Evaluation Board can be plugged on to these headers as shown in Figure 2.

     

    Figure 2. EZ-BLE PRoC Evaluation Board Plugged on BLE Pioneer Kit

    Figure 3 shows the pinout and details of the EZ-BLE PRoC Evaluation Board (CYBLE-212019-EVAL), which is a fan-out board for EZ-BLE PRoC Modules (CYBLE-212019-00).

    Figure 3. EZ-BLE PRoC Evaluation Board (CYBLE-212019-EVAL) Pinout

    The EZ-BLE PRoC Module exposes a subset of the GPIOs that are expected on the BLE Pioneer Kit. Therefore, the evaluation board for the module has several pins that do not map to any port of the module. In addition, some pins exposed on the J1 and J2 headers of the evaluation board differ from the pins expected on the J10 and J11 headers of the BLE Pioneer Kit. Table 1 shows the complete pin mapping and highlighting differences is shown below. Table 1 specifies NC (No Connect) for the pins that are not available on the evaluation board.

    Table 1. Complete Pin Mapping

    CY8CKIT-042-BLE

    J11 Header

    CYBLE-212019-EVAL

    J2 Header

     

    CY8CKIT-042-BLE

    J10 Header

    CYBLE-212019-EVAL

    J1 Header

    VDDD

    VDD*

     

    VDDA

    VDD[1]

    VREF

    VREF

     

    VDDR

    VDDR

    XRES

    XRES

     

    GND

    GND

    GND

    GND

     

    GND

    GND

    P0_0

    NC

     

    P2_0

    P2_0

    P0_1

    NC

     

    P2_1

    P0_5[2]

    P0_2

    NC

     

    P2_2

    P2_2

    P0_3

    NC

     

    P2_3

    P2_3

    P0_4

    NC

     

    P2_4

    P2_4

    P0_5

    NC

     

    P2_5

    P0_42

    P0_6

    P0_6

     

    P2_6

    P2_6

    P0_7

    P0_7

     

    P2_7

    P3_52

    P1_0

    P1_0

     

    P3_0

    NC

    P1_1

    NC

     

    P3_1

    NC

    P1_2

    NC

     

    P3_2

    P3_2

    P1_3

    NC

     

    P3_3

    P3_3

    P1_4

    P1_4

     

    P3_4

    P3_4

    P1_5

    P1_5

     

    P3_5

    P3_5

    P1_6

    P1_6

     

    P3_6

    P3_6

    P1_7

    P1_7

     

    P3_7

    P3_7

     

     

     

    P4_0

    NC[3]

     

     

     

    P4_1

    NC

     

     

     

    P5_0

    P5_0

     

     

     

    P5_1

    P5_1


     


    [1] EZ-BLE PRoC Module shorts the digital and analog power rails of PRoC BLE (highlighted rows in blue)

    [2] Pins differ from the pins expected on the BLE (highlighted rows in yellow)

    [3] The EZ-BLE PRoC Module has the P4_0 pin however this is connected to the Cmod capacitor on the EZ-BLE PRoC Evaluation Board and is not exposed on the J1 header.

     

    Note: The EZ-BLE PRoC Module is supported on PSoC® CreatorTM 3.3 SP1 and later versions. While the GPIOs available on the EZ-BLE PRoC Module and consequently on the EZ-BLE PRoC Evaluation Board are limited, every functionality available on a PRoC BLE silicon is available on the EZ-BLE PRoC Module. The only exception is the CapSense® Gestures Component that handles one- and two-finger gestures. This Component is not available on the EZ-BLE PRoC Module.

     

    Applicable Kits

     

                                                                    Table 2. Applicable Kits

     

    EZ-BLE PRoC Evaluation Board

    PRoC BLE Modules

    PSoC 4 BLE Modules

    CYBLE-212019-EVAL

    CY5671

    CY5674

    CY8CKIT-142

    CY8CKIT-141

    YES

    NO

    NO

    NO

    NO

             

    Headers (on CYBLE-212019-EVAL)

     

                                                                    Table 3. Usage Description

     

    Headers

    Usage Description

    J3

    Used to short VDDD and VDDR

    Note: J3 can be ignored for usage if customers insert CYBLE-212019-EVAL into CY8CKIT-042-BLE since VDDD and VDDR are short in CY8CKIT-042-BLE. However, if customers use the CYBLE-212019-EVAL separately, customer need to short J3 based on application requirement.

    J5

    P5.0 and P5.1 are available for debug purposes (no jumper usage intended here).

    J6

    Used to short P3.5 of CYBLE-212019-00 module to either/both of P3.5 and P2.7 of CY8CKIT-042-BLE.