Pin Mapping Differences Between the EZ-BLE™ PRoC™ Evaluation Board (CYBLE- 212019-EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE) - KBA10896

Version: **

 

Question:

What are the differences between the pins exposed on J1 and J2 headers of the EZ-BLE PRoC Evaluation Board (CYBLE- 212019-EVAL) and the pins expected by the J10 and J11 headers on the BLE Pioneer Kit (CY8CKIT-042-BLE)?

 

Answer:

Yes, there are differences between the pins exposed. The EZ-BLE PRoC Evaluation Board quick start guide explains how to use the board with the BLE Pioneer Kit and the differences in pin mapping. This is also explained below.

 

Figure 1 shows the J10 and J11 headers on the BLE Pioneer Kit.

 

1.png

 

Figure 1: J10 and J11 headers on BLE Pioneer Kit

 

The EZ-BLE PROC Evaluation Board can be plugged on to these headers as shown in Figure 2.

2.png

 

Figure 2: EZ-BLE PRoC Evaluation Board plugged on BLE Pioneer Kit

 

Figure 3 shows the pinout and details of the EZ-BLE PRoC Evaluation Board (CYBLE-212019-EVAL), which is a fan-out board for EZBLE PRoC Modules (CYBLE-212019-00).

 

3.png

 

Figure 3: EZ-BLE PRoC Evaluation Board (CYBLE-212019-EVAL) Pinout

 

The EZ-BLE PRoC Module exposes a subset of the GPIOs that are expected on the BLE Pioneer Kit. Therefore, the evaluation board for the module has several pins that do not map to any port of the module. In addition, some pins exposed on the J1 and J2 headers of the evaluation board differ from the pins expected on the J10 and J11 headers of the BLE Pioneer Kit. A table showing the complete pin mapping and highlighting differences is shown below. The table specifies NC (No Connect) for the pins that are not available on the evaluation board.

 

4.PNG

 

*EZ-BLE PRoC Module shorts the digital and analog power rails of PRoC BLE (highlighted rows in blue)
**Pins differ from the pins expected on the BLE (highlighted rows in yellow)
***The EZ-BLE PRoC Module has the P4_0 pin however this is connected to the Cmod capacitor on the EZ-BLE PRoC Evaluation Board and is not exposed on the J1 header.

 

Note: The EZ-BLE PRoC Module is supported on PSoC® CreatorTM 3.3 SP1 and later versions. While the GPIOs available on the EZ-BLE PRoC Module and consequently on the EZ-BLE PRoC Evaluation Board are limited, every functionality available on a PRoC BLE silicon is available on the EZ-BLE PRoC Module. The only exception is the CapSense® Gestures Component that handles one- and two-finger gestures. This Component is not available on the EZ-BLE PRoC Module.

 

Applicable Kits:

                                                                          

EZ-BLE PRoC Evaluation Board PRoC BLE Modules PSoC 4 BLE Modules
CYBLE-212019-EVAL CY5671CY5674CY8CKIT-142CY8CKIT-141
YESNONONONO

 

Headers (on CYBLE-212019-EVAL): Usage description

                                                            

HeadersUsage description
J3It is used to short VDDD and VDDR.
    Note: J3 can be ignored for usage if customers insert CYBLE-212019-EVAL into
    CY8CKIT-042-BLE since VDDD and VDDR are short in CY8CKIT-042-BLE.
    However, if customers use the CYBLE-212019-EVAL separately, customer need
    to short J3 based on application requirement.
J5P5.0 and P5.1 are available for debug purposes (no jumper usage intended
    here)
J6It is used to short P3.5 of CYBLE-212019-00 module to either/both of P3.5 and
    P2.7 of CY8CKIT-042-BLE.