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Translation - Japanese: PSoC® 3/ PSoC 5LP CPU か DMA で Verilog で PLD に実装されたコンポーネントからデータを取得する方法 - KBA203627 - Community Transl...
Question:
How can the CPU/DMA read from a Verilog component implemented in PLDs of UDB Blocks?
Answer:
There are no hardware registers associated with the PLD-based Verilog Component which can store the values of the signals used inside the Component. Therefore, the CPU/DMA cannot read directly from the Component. One way to read from the Component is to bring the required signals out through output pins and connect a status register to it.
Note: If a UDB Component PLD input or output associate to datapath fixed register by PI/PO bus, it also can be read by CPU/DMA. PI/PO bus shares the same 8-bit bus with the UDB status/control register.
A simple example of a 3-bit counter is as follows:
module Mod3Counter
(
count,
clock
);
output [2:0] count;
input clock;
//`#start body` -- edit after this line, do not edit this line
reg [2:0] count;
always @(posedge clock)
begin
count <= count+1'd1;
end
Endmodule
As can be seen, ‘count’ has an output signal. A status register connected to the ‘count’ terminal is shown below.
The CPU can read the counts by simply reading the status register. The counts can be transferred to another destination using DMA by setting the source address as the address of the status register.