Using Port D Pins as GPIO Pins when FX2LP is Configured in Slave FIFO Mode - KBA210880

Version 3

    Version: *A

     

    Translation - Japanese: FX2LPがスレーブFIFOモードで構成されている場合にポートDピンをGPIOピンとして使用する - KBA210880 - Community Translated (JA)

     

    Question:

    How can we use Port D pins as GPIO pins when FX2LP is configured in Slave FIFO mode?

     

    Answer:

    The Port D I/O pins of FX2LP can be configured for an alternative function – as the higher 8 bits of the Slave FIFO data bus. For more information, see the FX2LP Technical Reference Manual. To use the Port D pins as GPIO, all the FIFOs should be configured in 8-bit mode. This can be done by setting the WORDWIDE bit (bit 0 in the EPxFIFOCFG registers) as ‘0’. The sequence of commands to configure Port D as a GPIO is as follows.

     

    //Clear all WORDWIDE bits

     

    EP2FIFOCFG = 0x00; SYNCDELAY;

    EP4FIFOCFG = 0x00; SYNCDELAY;

    EP6FIFOCFG = 0x00; SYNCDELAY;

    EP8FIFOCFG = 0x00; SYNCDELAY;

     

    // Set part in Slave FIFO mode

     

    IFCONFIG = 0x43; SYNCDELAY; //set after WORDWIDE bits are cleared

     

    // PORTD can be configured as a GPIO

     

    Note: Ensure that FX2LP is set into Slave FIFO mode only after clearing all the WORDWIDE bits.