Importance of Coherency Registers – 16-Bit Data Transfer from ADC to DFB Using DMA in PSoC® 3 and PSoC 5 - KBA210684

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Question:

What is coherency byte in the ADC result, DFB staging, and DFB holding registers?

 

Answer:

The ADC result registers are protected on reads so that the underlying hardware does not update it when partially read by the CPU or DMA. When the CPU or DMA reads the 24-bit ADC result (3 bytes) as a multiple-byte read operation, it is possible for the ADC to overwrite the result register with new samples while the CPU or DMA is reading the current sample. To avoid this problem, the ADC module allows the user to specify the coherency byte using DEC_COHER[SAMP_KEY<1:0>] bits. If any byte of the ADC result register is read by the CPU or DMA, it will lock the result register from being overwritten until the coherency byte is read. Depending on the configuration of the block, not all bytes of the result registers may be needed.

The Digital Filter Block (DFB) provides two 24-bit staging registers for data input and two 24-bit holding registers for data output. The staging registers are protected on writes so the DFB does not incorrectly use the data when it is partially updated by the CPU or DMA. The holding registers are protected on reads so the DFB does not update it when partially read by the CPU or DMA. Depending on the configuration of the block, not all bytes of the staging and holding registers may be needed. The coherency methodology allows an output field of any size and handles it properly.

  • DFB_COHER[STGA_KEY<1:0>] bits specify the coherency byte for DFB Staging Register A
  • DFB_COHER[STGA_KEY<1:0>] bits specify the coherency byte for DFB Staging Register B
  • DFB_COHER[HOLDA_KEY<1:0>] bits specify the coherency byte for DFB Holding Register A
  • DFB_COHER[HOLDB_KEY<1:0>] bits specify the coherency byte for DFB Holding Register B

Refer to AN61102: PSoC 3 and PSoC 5LP – ADC Data Buffering Using DMA, which sets the ADC coherency to high bytes for 24-bit ADC data transfer through DMA. Note that by default, coherency is set to low byte.