How to operate QDR in PLL OFF mode and use CQ and CQ\ in QDR I mode?
During PLL OFF mode, QDR is bypassing the PLL. The CQ clock is not generated by the PLL but QDR is generating CQ directly from the input K clock. In addition, the output read data is generated with respect to the CQ clock only during the PLL OFF mode. The output data will be edge-aligned with CQ clock so you can use the CQ clock to capture the read data. As mentioned earlier that CQ clock has been generated from the K clock directly. If you want to use the CQ clock in QDR-I mode, you need to provide a stable K clock to QDR because it might affect the CQ clock as CQ clock is not generated from PLL.
Cypress recommends running QDR in the PLL OFF mode at <120 MHz. It is not recommended to run QDR with the PLL OFF mode at a higher frequency. In addition, note that the PLL OFF mode is not tested but guaranteed by design.