Interrupt Latency in PSoC® 1 - KBA88264

Version: **



What is the interrupt latency of a PSoC® 1 device? 



 Interrupt latency is the time between the assertion of an enabled interrupt and the start of its interrupt service routine (ISR). It is calculated using the following equation: 

Latency = Time to finish the current instruction +Time for M8C to change program counter to interrupt address +Time to execut e the LJMP instruction in the interrupt table 

For example, if the five-cycle JMP instruction is executing when an interrupt becomes active, the total number of CPU clock cycles before the ISR begins is as follows: 

(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine) + (7 cycles for LJMP) = 21 to 25 cycles. 

In this example, at 24 MHz, 25 clock cycles take 1.042 µs.