For asynchronous (or initial) access to flash pages, and for subsequent page mode accesses to already buffered page data, when will the data be valid for parallel NOR flash?
A first read access to a parallel NOR flash device requires an initial page access time to load one page of data from the flash memory cells to a RAM buffer (see the datasheet to find the page size for your device, as well as the initial access time). Subsequent accesses to the same page can be faster since the data is already present in the RAM buffer (see the datasheet for the page access time). The longer initial access time applies any time the next read accesses a new page.
For the initial page access the data valid time is related to the following AC characteristics:
- tACC - Address to Output Delay
- tCE - Chip Enable to Output Delay
- tOE - Output Enable to Output Delay
Data will be valid for an initial page access after all three of these AC characteristics are met.
Once the initial page read access is completed, if CE# and OE# remains LOW and address change can start a new access within the same page, then data will be valid tPACC (Page Access Time) after the address change.
For example in following waveform, the first data word (Data 0) will be valid after tACC, tCE, and tOE are met. Then when only A3-A0 (the offset within a page) are changed, the next data word (Data 1) will be valid after tPACC.
Best read performance can be achieved by configuring your host-side memory controller to use the page access time for all in-page read accesses, and the initial page access time for all reads to a new page.