Internal Routing of RESET# Signal on S71KL-S HyperFlash™/HyperRAM™ MultiChip Package (MCP) - KBA219070

Version 2

    Version: **



    Why is the RESET# signal not connected to the HyperRAM die in the S71KL-S HyperFlash/HyperRAM Multi-Chip package?



    In addition to resetting the flash, the RESET# signal on ball A4 is used on the HyperFlash die to enter a special test mode by putting a high voltage on that signal. The high voltage is not compatible with the HyperRAM die, so both RESET# signals cannot be connected to ball A4.


    The RESET# signal can be used on the discrete HyperRAM chip to do the following:


    • Return the device to the standby state
    • Cause the configuration registers to return to their default values
    • Halt the self-refresh operation while RESET# is LOW
    • Force the device to exit the Deep Power Down state


    To achieve the same results on the HyperRAM die that is part of the S71KL-S HyperFlash/HyperRAM MCP, the user must trigger a full power-on reset (POR) for the MCP. This is done by ensuring that when VCC drops below VLKO = 2.7 V that VCC then drops below VRST = 0.7 V for at least tPD = 50 µs before rising past VCC(MIN) = 2.7 V to the nominal operating range of 2.7 V–3.6 V. Note that the first access to the MCP should happen after tVCS = 300 µs elapses from the time VCC passes VCC(MIN). 1.png                                                                                                                

    VCC2.7 V–3.6 V2.7 V–3.6V
    VLKO2.7 V min2.4 V min
    VRST0.8 V min0.7 V min
    tPD50 µs min10 µs min
    tVCS300 µs max150 µs max