How do I use the DMA controller (DMAC) in FR81S MCUs?
When using the DMAC, confirm whether it supports transfer requests for peripherals such as UART, A/D, and PPG. This article introduces the following terms related to DMAC:
- Operating mode
- Transfer size
- Transfer trigger
- Transfer counts
- Transfer direction
- Transfer completion
- Operating mode of DMAC
DMAC has the following modes.
Single/Block transfer mode
This mode supports a one-time DMA transfer request. The transfer size is decided by the block size. For a large block size, the transfer rate improves, but actual throughput of the CPU decreases. Continuation transfer mode
This mode supports a DMA transfer while the transfer request (DREQ) is active. The CPU is assigned bus usage when the transfer counts register becomes ‘0’ or the DREQ input becomes inactive. Burst transfer mode This mode supports transferring a specified number of DMA transfer counts using one transfer request.CPU is assigned bus usage when the transfer counts register become ‘0’. Two-cycle type This mode is used to read and write by turns. In this type, a transfer occurs after the internal bus control has latched the data. Access can be of two types:
- Between internal area (RAM) and internal area (I/O)
- Between internal area (I/O) and external area (RAM)
Fly-by type This mode is used to read and write at the same time. In this type, transfers between external memory and external I/O can occur at the same time.
- Transfer size of DMAC
The DMAC transfer size is of three types:
- byte (8-bit)
- half-word (16-bit)
- word (32-bit)
Transfer trigger of DMAC
The DMAC transfer triggers include UART, SIO, A/D, PPG, and so on; it is different for each device. Refer to the respective hardware manuals for a list of DMA transfer requests.
Transfer counts of DMAC
Using the transfer counts register, it is possible to set the DMAC transfer counts in the range of 1 to 65536.The DMA transfer counts register is decremented by one for every transfer request.
Transfer direction of DMAC
The DMAC transfer is in the direction of transfer source address→ transfer destination address.These addresses can be increased or decreased, as required.
Transfer completion of DMAC
DMA transfer is complete when the specified transfer time is accomplished. You can set the interrupt to be available after the DMA transfer is complete.
An interrupt factor may occur if there is an error in the transfer request, such as a UART overrun. Make sure that there is no error causing an interrupt.