PSoC Creator 4.0 or previous version incorrectly allows a routing condition that causes a conflict between particular input pins and Digital Signal Interconnect (DSI) routing lines. This will most likely cause a design failure. Here are the conditions:
- PSoC 4 BLE design using the ADC_SAR_SEQ_P4 Component
- ADC_SAR_SEQ_P4 uses multiple channels
- A locked, hardware-driven digital output pin routed through the DSI shares the pin index with one of the ADC_SAR_SEQ_P4 inputs, and is in Port 2. So for example, the output pin is on Port 2, pin index 2 (P2) and an input to the ADC is on Port 3, pin index (P3). Note that this is unique to signals on Port 2 and Port 3 because of the DSI routing. (Yes, this is can be very confusing).
In PSoC Creator 4.1, you will see an error that looks like the following:
- E2713: cannot be placed at because the location does not support the required features: . The placer reported an error.
- E2055: An error occurred during placement of the design
- "C:\Program Files (x86)\Cypress\PSoC Creator\4.1\PSoC Creator\bin/sjplacer.exe" failed (0x00000001)
You may also see an error message such as “apr.M0003: Unable to find a solution for the analog routing”
The first thing to note is that PSoC Creator 4.1 will accurately report this conflict and not allow the design to build. Assuming, for this example, that you have the ADC input pin on P3 and a hardware digital output pin on P2, you can do one of the following:
- Unlock the pins (or unlock a set of pins) to allow the placer to find a legal solution
- Move the ADC input pin on P3 to another pin index in the ADC Port (P2 or P3 depending on your device).
- Similarly as in #2, you could move the digital output pin on P2 to another place such as P1 or P1, etc.
To change pin assignments or unlock pins - from the Workspace Explorer in PSoC Creator, go to the Pins tab in the Design-Wide Resource file ([project].cydwr). Notice that in the following screenshot, ADC_IN0 is on P3 (Port 3, pin index 2) and DIGITAL_PIN is on P2. To fix the conflict, you can either move ADC_IN0 to a different pin index in Port 3 or move DIGITAL_PIN to another pin index in Port 2 (or any available pin in another port).
More Technical Description:
When the ADC is configured to scan multiple channels using the dedicated hardware sequencer (i.e., with no CPU intervention required to change channels), the analog switches between the SAR and its input pins are placed into a “hardware controlled” model.
When in this mode, the switch will close if it receives a logic HIGH (1) value on either of two digital signals. The first signal is a dedicated control signal from the SAR Sequencer hardware. The second is a particular output line from the DSI.
The DSI line for each pair (one for vplus, one for vminus) of SAR input switches is shared and is also used for routing output signals from the DSI to one of the pins in port 2, even when the SAR is connected to port 3. The index of the pin to which the DSI is connected matches the index of the pin to which the SAR is connected. For example, the SAR input P3 would share its DSI control line with the DSI output line for P2.
Therefore, if the DSI output line for a pin in port 2 (P2) is driven HIGH, any hardware-controlled SAR switch which uses that line as a control signal connects that input pin to the SAR. If this were to occur at a time when the SAR was scanning a different input pin, it would cause the two inputs to become shorted, causing inaccurate ADC conversion results.