EZ-USB® HX3 I2C Slave Mode Operation – KBA90943

Version: *B

 

Question: What do you need to know about HX3 I2C slave mode operation?

 

Answer:

 

  1.   1. HX3 I2C Interface
     

       The HX3 I2C interface supports standard (100 kHz) and fast mode (400 kHz) frequencies.

  2.   2. Hardware Connection for I2C Slave Mode Operation
     

       2.1 Pull-Up on SDA and SCL Lines

     

       Both SDA and SCL signals require external pull-up resistors (2 kΩ). They are pulled up to the VDDIO (3.3 V) of HX3.

     

       2.2 MODE_SEL[1:0] Set to “2’b10”

     

       To select I2C slave boot mode, connect a pull-up resistor (10 kΩ) to MODE_SEL[1] and a pull-down resistor (10 kΩ) to the MODE_SEL[0] pins. Refer to the HX3 datasheet for details on configurations and boot options.Table 1 lists the boot configuration selection.

     
      

        Table 1. Boot Configuration Selection

      
                                                                                                                                                                                                                      
            MODE_SEL[1]        MODE_SEL[0]        HX3 Configuration Modes
           
             0
          
           
             0
          
            Reserved. Do not use this mode.
           
             1
          
           
             1
          
            Internal ROM configuration.
           
             0
          
           
             1
          
            I2C master, read configuration from I2C EEPROM.
           
             1
          
           
             0
          
            I2C slave, configure from an external I2C master.
      
     
  3.   3. I2C Slave Mode Operation
     

       In the I2C slave mode, HX3 is configured from an external I2C master. The design of the HX3 I2C slave protocol follows the standard I2C EEPROM protocol, which supports Random Write, Page Write, Random Read, and Sequential Read.

  4.   4. Multi-Slave Mode Operation
     

       Two HX3 hub controllers can be connected together in cascaded mode with I2C lines. An external processor can configure HX3s through the I2C bus independently. This mode is supported by connecting a pull-up or pull-down for pins DS3_LED_SS and DS4_AMBER. For the first HX3, DS3_LED_SS and DS4_AMBER are connected to logic LOW (pulled-down or floating); this can be configured in the 0xC0 I2C format. For the second HX3, DS3_LED_SS and DS4_AMBER are connected to logic HIGH (pulled-up using a 10-kΩ resistor); this can be configured in the 0xB0 I2C format.

     

       Note: DS3_LED_SS and DS4_AMBER are available only in the 88-pin QFN packages. Therefore, multi-slave mode operation using the DS3_LED_SS and DS4_AMBER controls cannot be used with the 68-pin QFN package devices.

  5.   5. I2C Format
     

       Similar to the I2C EEPROM, HX3 uses a 2-byte address cycle. However, HX3 does not use the WP, A2, A1, and A0 pins. By default, HX3 uses the 0xC0 I2C format. An alternative 0xB0 format is also available to support multi-slave mode by connecting both DS3_LED_SS and DS4_AMBER to logic HIGH (that is, connected to a pull-up).

     

       The HX3 I2C does not have any page size limit, but its internal RAM is limited to 16 KB. Therefore, I2C data should be limited to 16 KB. In other words, HX3 slave booting can be a stream byte of data, where the user can use a Page Write command to send the entire file, up to 16 KB.

     

       HX3 can use two types of payloads, as explained in the following sub-sections: 0xD4 Format and 0XB0 Format. The configuration file in both formats can be generated by using the Cypress-provided I2C configuration tool (Blaster Plus). To use the I2C slave mode, Cypress recommends using the Blaster Plus tool to generate the configuration file and loading it to HX3 through the I2C interface.

     

       5.1 0xD4 Format

     

       HX3 can load customized configurations such as battery charging configurations, port controls, PHY parameters, and custom VID/PID. The 0xD4 format is used for customized configurations.

     

       5.2 0xB0 Format

     

       HX3 supports the ARM® Cortex™-M0 CPU with 16 KB ROM and 16 KB RAM. Custom firmware (with or without customized configurations) can be loaded to the HX3 RAM using this format in the I2C slave mode. This mode should not be used unless Cypress has recommended to the use of special external firmware. Refer to the HX3 datasheet for more details on I2C data formats and configuration options.

  6.   6. Sample I2C Subroutiness
     

       6.1 0xD4 Format I2C Subroutine

     

       i2c_page_write(int address, char *buff, int length);

     

       Where:

     
        
    •     address: internal byte control format: 0xC0 or 0xB0
    •   
    •     buff: content of the 0xD4 configuration structure
    •   
    •     length: the total length of the 0xD4 configuration (between 11-197)
    •  
     

       After executing the code i2c_page_write(0xC0, buff, 197), it will generate the following cycles on the I2C bus:

     
       START bit 0xC0, 0x00, 0x00, 0x43, 0x59, 0x30, 0xD4, 192, bytes of buff[5-196], STOP BIT.
     

       6.2 0xB0 Format I2C Subroutine

     

       i2c_page_write(int address, char *buff, int length);

     

       Where:

     
        
    •     address: internal byte control format: 0xC0 or 0xB0
    •   
    •     buff: content of the 0xB0 configuration structure
    •   
    •     length: the total length of the 0xB0 configuration should be less than 16 KB
    •  
     

       After executing this code i2c_page_write(0xC0, buff, sizeof(buff)), it will generate the following cycles on the I2C bus:

     
      START bit 0xC0, 0x00, 0x00, 0x43, 0x59, 0x30, 0xD4, 192, bytes of buff[5-sizeof(buff)], STOP BIT.