How do I configure SX2 for streaming data through bulk or isochronous endpoints?
EZ-USB SX2 is a serial interface engine (SIE)–only device without any RAM for code download. It needs an external master to initialize its registers and enable the device to enumerate. SX2 only buffers the data from the peripheral and sends it to the host over USB and vice versa. SX2 cannot modify the data received from either the peripheral or the host before committing it to the destination. By configuring the endpoints appropriately in SX2, it can be enabled to stream data to/from the external master from/to the USB Host. Streaming data through SX2 is equivalent to streaming data through EZ-USB FX2LP configured for Slave AUTO mode operation.
Endpoints in SX2
SX2 supports one control endpoint (EP0) and four configurable data endpoints (EP2, EP4, EP6, and EP8), like EZ-USB FX2LP, and occupies the dedicated endpoint RAM. Data endpoints are configurable as bulk, interrupt, or isochronous; double, triple, or quad buffered endpoints sharing the 4-KB FIFO buffer space (Figure 1).
Figure 1. High-Speed Endpoint Configurations
The default endpoint memory configuration at power-on reset is as follows:
- EP2: Bulk OUT, 512 bytes, 2x buffered
- EP4: Bulk OUT, 512 bytes, 2x buffered
- EP6: Bulk IN, 512 bytes, 2x buffered
- EP8: Bulk IN, 512 bytes, 2x buffered
Endpoint register configuration
SX2 contains configuration registers that control the size, length, and direction of its endpoint buffers. The external master has to write the appropriate values into these registers for the endpoints to function according to the descriptors. For example, to configure Endpoint 2 as an IN endpoint, in addition to writing the descriptors for Endpoint 2 appropriately, the SX2 command register EP2CFG has to be written with a corresponding value to configure the direction of the SX2 Endpoint 2 buffer as IN. For a list of the SX2 registers, refer to the SX2 datasheet.
Consider one example endpoint configuration as follows:
- Endpoint 2: Bulk OUT, 512 bytes, 2x buffered in high-speed mode
- Endpoint 4: Bulk IN, 512 bytes, 2x buffered in high-speed mode
- Endpoint 6: Interrupt IN, 1024 bytes, 2x buffered in high-speed mode
The values to be written into the registers to achieve this configuration follow (note that the register names as given in the SX2 datasheet are listed as comments alongside the values):
0xAA, //IFCONFIG // MHz=1=48 ASYNC=1 FLAGD=1
0xA8, //FLAGA - fixed EP2EF, FLAGB - fixed EP6EF
0xFD, //FLAGC - fixed EP4FF, FLAGD - fixed EP8FF
0x00, //POLAR // all signals active low
0xA2, //EP2CFG // Set Dir OUT
0xE0, //EP4CFG // Set Dir IN
0xFA, //EP6CFG // Set Dir IN
0x00, //EP8CFG // Invalid Endpoint
0x02, //EP2PKTLENH // Zerolen=0 Wordwide=0
0x02, //EP4PKTLENH // Zerolen=0 Wordwide=0
0x22, //EP6PKTLENH // Zerolen=1 Wordwide=0
0x22, //EP8PKTLENH // Zerolen=1 Wordwide=0
Similarly for isochronous endpoint configuration, the appropriate values must be set for the corresponding EPxCFG register. Refer to the SX2 datasheet for the EPxCFG register field definitions.
Note: SX2 was not designed to support dynamic modification of these endpoint configuration registers. If the application needs the ability to change endpoint configurations after the device has already enumerated with a specific configuration, expect some delay in accessing the FIFOs after changing the configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 µs, measured from the time the READY signal is asserted, before writing to the FIFO. This delay varies for different registers and is not specified.
SX2 can successfully enumerate with the required endpoint configuration after the appropriate values are written to the SX2 configuration registers and the descriptors are loaded into SX2.
The payload data to the external master is automatically transferred from the USB domain to the peripheral or interface domain and transferred over the Slave FIFO interface under the control of the external master. Similarly, the payload data sent by the external master to SX2 over the Slave FIFO interface is automatically transferred to the USB domain from the peripheral or interface domain. The slave FIFO architecture uses the endpoints (in the endpoint RAM) as FIFO memories that are controlled by FIFO control signals (IFCLK, CS#, SLRD, SLWR, SLOE, PKTEND, and FIFOADR[2:0]). SX2 has three address pins (FIFOADR[2:0]) that are used to select either the FIFOs or the command interface (Table 1). Refer to the SX2 datasheet for further details on how to access the Slave FIFO interface (synchronously or asynchronously) from the external master.
Table 1. FIFO Address Line Settings
Thus, correct endpoint configuration and correct addressing from the external master to select the appropriate endpoint will enable seamless data streaming through that endpoint.
Refer to other Knowledge Base Articles on SX2 here.