Yes, it is possible to use FX2 for the application described above. Mode 2 would be relatively straightforward considering that we have a reference design for this very purpose.
For mode 1, here are some of the design considerations:
1) If the FIFO/RAM is connected to the address/data bus of the 68013 let's say, you could have separate code (from Mode 2) running that knows how to take the contents of the FIFO/RAM and transfer it to the IDE drive.
2) See page 10-58 of the FX2 Technical Reference Manual, and you'll find that in point 3., the contents of the FIFO buffer can be edited manually. Then you could launch the GPIF transaction with those contents. However, you'll need some kind of flag to alert the firmware that this happens because FX2 is not connected to the USB bus. This event may be a status pin from the FIFO/RAM that the FX2 firmware detects.
3) Consider using the Slave FIFO interface instead of the address/data bus. The IDE drive data bus must be tri-stated. You could write data into the Slave FIFO (e.g. 512 bytes), switch to GPIF mode by writing to the appropriate bits in the IFCONFIG register, then launch the GPIF transaction to burst the data out to the IDE drive. This mode of operation was something that was not simulated, so unfortunately we cannot guarantee this operation. However, all indications are that it should work. For performing this operation, it is recommended that the FX2 stay in manual mode so that the CPU has full control of committing the data packets (like in page 10-58 of the Technical Reference Manual).
The Slave FIFO interface would be a lot faster than the regular CPU address/data bus, so this would be the fastest method to pump data through. For an estimate of the bandwidth numbers over the address/data bus interface, please refer to page 12-6 in the FX2 TRM. At 48MHz, you would be able to achieve about 23MB/s over the address/data bus.