R/B pins for the CY7C68023

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    Question: What is the functionality of multiple R/B pins in CY7C68023?



    The NX2LP has two R/B pins to support a protocol known as "interleave". This allows the NX2LP to work with a different NAND flash chip (or die in a chip) while another is busy. When interleave is not used (almost all cases), both of the R/B signals on the NX2LP need to be tied together so that proper ready/busy operation is detected.