Translation - Japanese: SPI NVSRAMのHOLD*ピンについて- Community Translated (JA)
Should any line (Serial Input-SI, Serial Output-SO or Clock-SCK) be pulled LOW when HOLD* (Active Low) pin is asserted in Serial NVSRAMs?
To assert HOLD* pin, SCK should be brought LOW first. When HOLD* is asserted (brought LOW), then Serial transfer is supended/paused and without resetting the ongoing SPI communication. In this situation, input on SI line is ignored and SO line goes in high Impedance state. During the HOLD* signal is asserted, SCK line may also toggle. When the HOLD* signal is de-asserted (bring it to high) to resume suspended SPI communication, the SCK must be brought low prior to bringin HOLD* high.