What is the significance of the Write Enable Latch (WEL) bit in the status register of serial SPI FRAM and the Write Enable (WEN) bit in the status register of serial SPI nvSRAM?
Let’s consider a serial SPI FRAM. Before any write operation (e.g., writing to the status register or to the memory), the WREN command must be issued. Sending the WREN opcode sets the internal write enable latch, which is indicated by the WEL flag in the status register. WEL=1 indicates that the writes are permitted. Attempting to write the WEL bit in the status register has no effect on the state of this bit. WEL is automatically cleared on the rising edge of /CS at the end of a write operation. Therefore, it prevents further writes to the status register or to the memory without another WREN command. You can manually clear the WEL bit by issuing a Write Disable (WRDI) opcode.
In addition, please note that reading the status register (RDSR opcode) between the WREN and WRITE opcodes will not clear the WEL bit. Therefore, some users read the status register immediately following the WREN to check that the WEL bit is set. However, reading the WEL bit is not required to complete the write operation.
The same explanation applies to serial SPI nvSRAM. Please note that Bit 1 of the status register is designated as WEL in the case of serial SPI FRAM and is designated as WEN in the case of serial SPI nvSRAM.