How many external components can be reduced by migrating from CCG1 Type-C controller to CCG2 Type-C controller for a Type-C cable application?
In a single-chip EZ-PD CCG1-based cable solution, we need 11 resistors, 5 capacitors, 2 diodes and 2 FETs, whereas in single-chip EZ-PDCCG2-based cable design, we need only 1 resistor and 4 capacitors.
In a dual-chip EZ-PD CCG1-based cable solution (one chip per Type-C plug), we need 22 resistors, 10 capacitors and 4 FETs whereas for a dual-chip EZ-PD CCG2-based cable design, we need only 2 resistor and 6 capacitors. Refer to the following tables for more details.
|Single Chip Cable|
|Dual Chip Cable|
For designing Type-C cables using CCG2, refer to the application note AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™ CCG2.
Question: How do I route traces for EZ-PD CCG1 and EZ-PD CCG2 using High Density Interconnect (HDI)?
Answer: AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2 discusses the layout recommendations and constraints for the CSP package of EZ-PD CCG1 and EZ-PD CCG2 devices. These guidelines help to ensure the best performance with respect to signal integrity and full electrical compliance with the USB Power Delivery and Type-C specification.
Question: Does CCGx Type-C controller support Over Voltage Protection (OVP) and Over Current Protection (OCP) features?
Answer: Cypress’s EZ-PD CCG1 supports OVP using an internal ADC and needs external hardware to detect overcurrent situation. However, both the features are enabled in firmware by default. Refer to CY4501 development kit schematic for more details on the hardware required to enable these features.
Cypress’s EZ-PD CCG2 needs external hardware to detect both the OVP and OCP; by default, these features are not enabled in the firmware. For implementing these features in the firmware and for the schematics, Contact Cypress Tech support.
Question: What can be the maximum trace length of the CC line?
Answer: In any USB system, the trace length of the CC line is constrained by the trace lengths of USB SuperSpeed (SS) and USB HiSpeed (HS) signals because they share the same connector. The CC signal of the USB Type-C is much lower in frequency (330 kHz max) compared to the SS and HS signals and therefore, there is no critical limitation with respect to the CC signal trace length.
Question: What is the function of the VREF pin in EZ-PD CCG1 Notebook Solution?
Answer: The CC signal is an analog signal, but carries digital values. Therefore, we need to compare the CC signal against a reference to determine if it is a ‘0’ or a ‘1’. The VREF pin in the EZ-PD CCG1-based Notebook Design is used to provide this reference to compare the CC signal.
Question: How can I to monitor the signal on the CC line communication with the CY4501 DVK?
Answer: The CY4501 Kit (Rev 06) provides external debug headers to monitor the CC line traffic. On the CCG1 host board, pins 8 and 12 from jumper J2 can be used to monitor CC2 and CC1 respectively. Similarly on the CCG1 client board, pins 8 and 12 from jumper J4 can be used to monitor CC2 and CC1 respectively. The CC pin of either host or client board needs to be connected to the sniffer, which can decode the CC messages.
The design files of the CY4501 CCG1 development kit are available in the following website link http://www.cypress.com/documentation/development-kitsboards/cy4501-ccg1-development-kit