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Introduction

 

The following blog demonstrates a setup for conducting throughput test with coexistence enabled. The results of the conducted tests are also included thereby demonstrating the advantages of using coexistence. 2-wire SECI is used in this test for exchanging coexistence data among the two Cypress chips. More about SECI could be found in the following link: Overview of SECI.

 

The applications and the platforms used for throughput test are :

  1. Iperf application running in CYW943907WAE4
  2. Le_COC throughput application running in CYW20719Q40EVB_01(attached)

 

 

Connections

The diagram below depicts the pins and connections between the two boards:

image1.png

 

 

Setting up CYW20719Q40EVB_01:

 

Any of the available(pins that are brought out in the platform) LHL GPIO pins can be configured to function as SECI. The LHL GPIOs WICED_P10 and WICED_P06(mapped to A0 and D8 respectively on CYW20719Q40EVB_01 ) are used as BT_SECI_OUT and BT_SECI_IN respectively in the attached BT throughput application.

To configure the LHL GPIOs as SECI, the following API is used:

 

wiced_bt_gpio_select_status_t wiced_hal_gpio_select_function(wiced_bt_gpio_numbers_t pin, wiced_bt_gpio_function_t function);

 

Eg: for configuring the LHL GPIOs, WICED_P10 and WICED_P06 as BT_SECI_OUT and BT_SECI_IN

 

wiced_hal_gpio_select_function(WICED_P10 , WICED_GCI_SECI_OUT);

wiced_hal_gpio_select_function(WICED_P06 ,WICED_GCI_SECI_IN );

 

And finally to enable coexistence in BT, the following API is used:

wiced_result_t wiced_bt_coex_enable( uint32_t seci_baud_rate );

 

Seci baud rate can be set to a maximum of 4M. In the attached example application, a baudrate of 3M is used.

Eg:

wiced_bt_coex_enable(3000000);

 

The following code pic depicts the usage of the above mentioned APIs:

bt_coex_code.png

Finally flash the application on the BLE GATT server( CYW20719Q40EVB_01 ), and connect the device to a BLE client. CySmart BLE 4.2 USB dongle was used as the client in this throughput test. Make sure to enable notifications from the server, in the client using the CySmart application.

Setting up CYW943907WAE4 :

 

Change the last bit/LSB of boardflags parameter in the nvram.txt to 1.

Each boardflags parameter is 32 bit wide. The LSB corresponds to switching the BTCOEX.

Eg;

Boardflag=0x0a0 => boardflags = 0x0a1

Following commands were used to setup the iperf in the AP and STA.

 

AP as UDP client(tx):

wl mpc 0

wl up

wl frameburst 1

start_ap tput open 0102 6 255.255.255.0 192.168.1.100

iperf -c 192.168.1.101 -u -i1 -t10 -w8m -b10m

AP as TCP client(tx):

iperf -c 192.168.1.101 -i1 -t10 -w8m

 

STA as UDP  server(rx):

wl mpc 0

wl up

join tput open 0102 192.168.1.101 255.255.255.0 192.168.1.100

iperf -s -u -i1 -8k

STA as TCP  server(rx):

iperf -s -i1 -8k

 

Finally throughput results here:

BLE and wifi thoughput without coexistence

UDP and TCP without BT interference and coex disabled

wifi data without BT interference and coex enabled

 

 

UDP throughput without BLE interference

 

[ ID] Interval       Transfer     Bandwidth        Jitter Lost/Total Datagrams

[  0] 0.0- 1.0 sec  1.20 MBytes  10.0 Mbits/sec   0.918 ms 0/  853 (0%)

[  0] 1.0- 2.0 sec  1.18 MBytes  9.93 Mbits/sec   0.949 ms 6/  850 (0.71%)

[  0] 2.0- 3.0 sec  1.19 MBytes  9.96 Mbits/sec   1.210 ms 2/  849 (0.24%)

[  0] 3.0- 4.0 sec  1.19 MBytes  10.0 Mbits/sec   0.982 ms 0/  852 (0%)

[  0] 4.0- 5.0 sec  1.19 MBytes  9.95 Mbits/sec   0.984 ms 3/  849 (0.35%)

[  0] 5.0- 6.0 sec  1.19 MBytes  9.97 Mbits/sec   1.407 ms 2/  850 (0.24%)

[  0] 6.0- 7.0 sec  1.18 MBytes  9.89 Mbits/sec   1.526 ms 4/  845 (0.47%)

[  0] 7.0- 8.0 sec  1.19 MBytes  9.95 Mbits/sec   1.005 ms 10/  856 (1.2%)

[  0] 8.0- 9.0 sec  1.19 MBytes  10.0 Mbits/sec   1.134 ms 0/  850 (0%)

[  0] 9.0-10.0 sec  1.19 MBytes  9.97 Mbits/sec   0.790 ms 3/  851 (0.35%)

[  0] 0.0-10.0 sec  11.9 MBytes  9.95 Mbits/sec   1.179 ms 31/ 8507 (0.36%)

 

 

TCP throughput without BLE interference and coex disabled

 

[  0]  0.0- 1.0 sec  1.01 MBytes  8.47 Mbits/sec

[  0]  1.0- 2.0 sec  1.12 MBytes  9.36 Mbits/sec

[  0]  2.0- 3.0 sec  1020 KBytes  8.36 Mbits/sec

[  0]  3.0- 4.0 sec   947 KBytes  7.76 Mbits/sec

[  0]  4.0- 5.0 sec   859 KBytes  7.04 Mbits/sec

[  0]  5.0- 6.0 sec  1.11 MBytes  9.31 Mbits/sec

[  0]  6.0- 7.0 sec  24.4 KBytes   200 Kbits/sec

[  0]  7.0- 8.0 sec  14.3 KBytes   117 Kbits/sec

[  0]  8.0- 9.0 sec  9.98 KBytes  81.8 Kbits/sec

[  0]  9.0-10.0 sec  4.28 KBytes  35.0 Kbits/sec

[  0]  0.0-10.8 sec  6.05 MBytes  4.70 Mbits/sec

 

UDP throughput with BLE interference and coex disabled

 

[ ID] Interval       Transfer     Bandwidth        Jitter   Lost/Total Datagrams

[  0]  0.0- 1.0 sec   680 KBytes  5.57 Mbits/sec   4.734 ms  166/  640 (26%)

[  0]  1.0- 2.0 sec   111 KBytes   906 Kbits/sec   2.146 ms   41/  118 (35%)

[  0]  2.0- 3.0 sec  1.44 KBytes  11.8 Kbits/sec  74.137 ms   30/   31 (97%)

[  0]  3.0- 4.0 sec   375 KBytes  3.07 Mbits/sec   1.105 ms    0/  261 (0%)

[  0]  4.0- 5.0 sec   996 KBytes  8.16 Mbits/sec   3.488 ms   25/  719 (3.5%)

[  0]  5.0- 6.0 sec   291 KBytes  2.39 Mbits/sec   9.384 ms  283/  486 (58%)

[  0]  6.0- 7.0 sec   502 KBytes  4.12 Mbits/sec   6.382 ms    0/  350 (0%)

[  0]  7.0- 8.0 sec   601 KBytes  4.93 Mbits/sec   2.328 ms    5/  424 (1.2%)

[  0]  8.0- 9.0 sec  1.26 MBytes  10.5 Mbits/sec   0.854 ms    4/  901 (0.44%)

[  0]  0.0-10.0 sec  5.86 MBytes  4.94 Mbits/sec   1.252 ms  555/ 4736 (12%)

 

Observable packet drops seen in Wifi due to interference from  BLE

 

TCP throughput with BLE interference

 

[  0] 0.0- 1.0 sec  29.9 KBytes   245 Kbits/sec

[  0] 1.0- 2.0 sec   369 KBytes  3.03 Mbits/sec

[  0] 2.0- 3.0 sec   605 KBytes  4.96 Mbits/sec

[  0] 3.0- 4.0 sec  21.0 KBytes   172 Kbits/sec

[  0] 4.0- 5.0 sec   247 KBytes  2.03 Mbits/sec

[  0] 5.0- 6.0 sec   490 KBytes  4.01 Mbits/sec

[  0] 6.0- 7.0 sec  9.98 KBytes  81.8 Kbits/sec

[  0] 7.0- 8.0 sec  3.82 KBytes  31.3 Kbits/sec

[  0] 8.0- 9.0 sec  1.89 KBytes  15.5 Kbits/sec

[  0] 9.0-10.0 sec  8.55 KBytes  70.1 Kbits/sec

[  0] 10.0-11.0 sec  0.00 Bytes 0.00 bits/sec

[  0] 11.0-12.0 sec  2.85 KBytes 23.4 Kbits/sec

[  0] 12.0-13.0 sec  1.43 KBytes 11.7 Kbits/sec

[  0] 13.0-14.0 sec  4.28 KBytes 35.0 Kbits/sec

[  0] 0.0-14.3 sec  1.76 MBytes  1.03 Mbits/sec

 

UDP throughput with coex enabled

 

[  0] 0.0- 1.0 sec  1.20 MBytes  10.0 Mbits/sec   1.067 ms 0/  853 (0%)

[  0] 1.0- 2.0 sec  1.12 MBytes  9.36 Mbits/sec   0.895 ms 2/  798 (0.25%)

[  0] 2.0- 3.0 sec  1024 KBytes  8.38 Mbits/sec   1.135 ms 21/  734 (2.9%)

[  0] 3.0- 4.0 sec  1.26 MBytes  10.5 Mbits/sec   0.842 ms 2/  898 (0.22%)

[  0] 4.0- 5.0 sec  1.16 MBytes  9.76 Mbits/sec   0.985 ms 8/  838 (0.95%)

[  0] 5.0- 6.0 sec  1002 KBytes  8.21 Mbits/sec   0.952 ms 10/  708 (1.4%)

[  0] 6.0- 7.0 sec  1.40 MBytes  11.7 Mbits/sec   0.944 ms 28/ 1025 (2.7%)

[  0] 7.0- 8.0 sec  1.20 MBytes  10.1 Mbits/sec   1.131 ms 10/  865 (1.2%)

[  0] 8.0- 9.0 sec  1.09 MBytes  9.17 Mbits/sec   1.257 ms 4/  784 (0.51%)

[  0] 9.0-10.0 sec  1.24 MBytes  10.4 Mbits/sec   1.130 ms 25/  912 (2.7%)

[  0] 0.0-10.0 sec  11.6 MBytes  9.75 Mbits/sec   1.435 ms 111/ 8417 (1.3%)

 

 

TCP throughput with coex enabled

 

[  0] 0.0- 1.0 sec  3.55 MBytes  29.7 Mbits/sec

[  0] 1.0- 2.0 sec  3.61 MBytes  30.3 Mbits/sec

[  0] 2.0- 3.0 sec  3.46 MBytes  29.1 Mbits/sec

[  0] 3.0- 4.0 sec  3.05 MBytes  25.6 Mbits/sec

[  0] 4.0- 5.0 sec  16.4 KBytes   134 Kbits/sec

[  0] 5.0- 6.0 sec  2.14 KBytes  17.5 Kbits/sec

[  0] 6.0- 7.0 sec  2.02 MBytes  16.9 Mbits/sec

[  0] 7.0- 8.0 sec  2.93 MBytes  24.6 Mbits/sec

[  0] 8.0- 9.0 sec  1.42 MBytes  11.9 Mbits/sec

[  0] 9.0-10.0 sec  3.47 MBytes  29.1 Mbits/sec

[  0] 0.0-10.0 sec  23.5 MBytes  19.7 Mbits/sec

 

 

BLE throuhgput when coex not enabled

BT_activity_without_coex.png

BLE througput with coex enabled

 

BT_activity_with _coex.png

 

Inference:

 

Given the low priority setting for the BT custom profile(for client-server notification), the throughput saw a observable improvement in WiFi side and at the same time the BT side experienced a heavy throughput loss.

VinayakS_26

Overview of SECI

Posted by VinayakS_26 Moderator Apr 3, 2018

Introduction

The WLAN(802.11b/g/n), Bluetooth and Zigbee transmissions occur in the unlicensed ISM (The industrial, Scientific, and Medical) radio bands of 2.4GHz. Although they are modulated with different modulation schemes (FHSS for BT and DSSS/OFDM for WLAN), interference is bound to occur when the transmitting antennas are collocated. BT could hop into the WLAN band resulting in an exponential backoff before retransmission of packets. This degrades the performance of both BT as well as WLAN. Collaborative coexistence techniques remedies this issue by passing the channel map information from the WLAN module to the BT device.

This blog gives a brief description about the Cypress Proprietary Collaborative coexistence interface known as SECI (Serial Enhanced Coexistence Interface) and enabling it using cypress WLAN and Bluetooth devices

SECI uses the UART core(commonly named as GCI UART) to transmit ECI data. 64-bit coexistence data could be exchanged between WLAN and BT. As a result, a lot more information is passed on between the devices compared to its counterparts i.e. 3-wire and 4-wire coexistence. A refresh routine runs, that resyncronizes the devices upon waking from powersave.

The following is a logical diagram of SECI between two devices.

secipic.jpg

 

How to enable SECI in WLAN

 

Steps involved and their descriptions:

  • Modify the LSB(bit[0]) of  boardflags parameter in the NVRAM file.

To enable 2-wire(SECI) coexistence, set the last bit(bit[0]) as 1.

Eg: if boardflags=0x10010000   ->  boardflags=0x10010001

How to enable SECI in Bluetooth side

 

Adding the API wiced_bt_coex_enable() in the application, enables the SECI in BT device.

 

Frequently Asked Questions

 

Is there a concept of AFH in collaborative coexistence?

The Adaptive Frequency Hop information is not passed back to WLAN, rather WLAN module passes information on current WLAN transmit channels. BT marks them as ‘bad’ and updates the channel map.

 

What information is exchanged?

Timeout parameters(egACL,SCO timeout limits, Powersave/idle times, Medium Request/Grant times) ,

Channel bitmap,

Priority of WLAN/BT activity bitmap, etc. are the some of the information that are exchanged.

 

Can the priorities be changed?

The priorities cannot be changed. It is hardcoded.

Generally, the highest priority goes to Audio/Video/BLE/hid transfer. File transfer has the least activity.

 

Configuring sLNA or dLNA?

Cannot be changed dynamically even though NVRAM parameters exists as it in Hardware.

 

What happens during WiFi powersave?

During Wifi powersave, all the requests from Bluetooth are given full grant. This is applicable for both sLNA and dLNA. Once WiFi comes out of powersave, it runs a refresh request to notify BT that it is awake. This restarts all the coex polls between WiFi and BT.

VinayakS_26

XIP support in CYW4390x

Posted by VinayakS_26 Moderator Mar 28, 2018

This blog presents the steps needed to enable XIP(eXecute-In-Place) support in CYW4390x. During normal operation, the code resides in the SFLASH and is copied to RAM during execution.The XIP feature allows instructions stored in SFLASH to be executed in place. This is suitable for instances where the RAM size is limited and application size is too large.

 

How to enable XIP

 

XIP feature is disabled by default and it can be easily enabled by adding 'xip' option to build target,

for example:

snip.scan-CYW943907AEVAL1F-xip download run

 

XIP load address, link script start address as well as XIP region length are defined in $PLATFORM/platform_xip.mk and it's configurable by users.

The following macros needs to be defined to enable XIP.

  • XIP_LINK_START_ADDRESS  : Specify the start address of XIP in linker script
  • XIP_REGION_LENGTH            : Specify the length of XIP region in linker script
  • XIP_LOAD_ADDRESS              : Specify the XIP SFLASH address. XIP binary code would be downloaded to  this address.

 

 

XIP link script:WICED/platform/MCU/BCM4390x/GCC/app_without_rom_with_xip.ld will be generated based on platform_xip.mk and its processed through the build process.

XIP binary file: *.xip.bin which contains XIPed code will be generated in build/$APP/binary/ and loaded to SFLASH.

All XIP code on SFLASH should be contiguous.

 

Limitations while using XIP

  1. XIP operation and SFLASH access are NOT allowed to operate simultaneously. SFLASH read/write(non-xip) operation can only run with interrupts disabled.
  2. The XIP image cannot be encrypted because the SFLASH controller has no HW decryption engine.
  3. OTA2 is not yet supported while using XIP.
VinayakS_26

CYW43907 GPIO Explained

Posted by VinayakS_26 Moderator Dec 29, 2017

This  blog discusses about the General Purpose Input Output (GPIO) available in CYW43907.

There are 17 GPIO hardware pins available on the CYW43907. The GPIOs can be used to connect to various external devices. Upon power-up and reset, these pins are tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other functions.These functions can be found in the Pin multiplexing table in CYW43907 datasheet(Section 11). Apart from the functions mentioned in the pin multiplexing table, GPIOs are also used to set bootstrap functions. JTAG pins are also multiplexed onto GPIO.

 

PIN MULTIPLEXING TABLE

After power-on reset, all the Pins are configured to function 1. There are 32 GPIO functions (GPIO_0 TO GPIO_31)  in total and the 17 hardware GPIO pins are configured to  GPIO functions GPIO_0 through GPIO_16. Following table shows GPIO Pin Multiplexing (Excerpt from CYW43907 Data Sheet).

 

mux_table1.jpg

 

The other pins that have GPIO functionality could be seen from the PIN MULTIPLEXING table. They can also be configured to function as a GPIO using the API; wiced_gpio_init()(Described below). Note that this is possible only for those Pins which have GPIO function.

mux_table3.jpg

For example, in the above table, PWM3 has GPIO function GPIO_5 and GPIO_21.

 

 

Relevant API's and Description:

On CYW943907AEVAL1F, all the pins are referred as WICED_GPIO_1 through WICED_GPIO_51. Refer the pin mapping in the platform located inside of WICED Studio at:

/43xxx_Wi-Fi/platforms/CYW943907AEVAL1F/platform.c

API documentation included as part of WICED Studio covers these APIs in great detail, here is high-level description of APIs available for GPIOs for this device.

 

1. wiced_result_t wiced_gpio_init( wiced_gpio_t gpio, wiced_gpio_config_t configuration )

Description: To initialize a pin as GPIO. Note that this is possible only for those pins that have GPIO functionality listed in the PIN MULTIPLEXING table. For those pins that have multiple GPIO functionality, the first GPIO function will be invoked. The pin to be configured as GPIO along with the configuration is passed to the API.

The possible configurations are :

GPIO ConfigurationsDescriptions
INPUT_PULL_UPInput with an internal pull-up resistor - use with devices that actively drive the signal low - e.g. button connected to ground
INPUT_PULL_DOWNInput with an internal pull-down resistor - use with devices that actively drive the signal high - e.g. button connected to a power rail
OUTPUT_PUSH_PULLOutput actively driven high and actively driven low - must not be connected to other active outputs - e.g. LED output
INPUT_HIGH_IMPEDANCEInput - must always be driven, either actively or by an external pullup resistor
OUTPUT_OPEN_DRAIN_NO_PULLOutput actively driven low but is high-impedance when set high - can be connected to other open-drain/open-collector outputs. Needs an external pull-up resistor
OUTPUT_OPEN_DRAIN_PULL_UPOutput actively driven low and is pulled high with an internal resistor when set high - can be connected to other open-drain/open-collector outputs.

 

2. wiced_result_t wiced_gpio_output_high( wiced_gpio_t gpio ):

Description: To toggle the configured GPIO pin high.

 

3. wiced_result_t wiced_gpio_output_low( wiced_gpio_t gpio ):

Description: To toggle the configured GPIO pin low.

 

4. wiced_bool_t wiced_gpio_input_get( wiced_gpio_t gpio ):

Description: To configure the GPIO pin as an input pin.

 

5. wiced_result_t wiced_gpio_deinit( wiced_gpio_t gpio ):

Description: To de-initialize the configured GPIO pin.

VinayakS_26

SPI in CYW43907

Posted by VinayakS_26 Moderator Dec 27, 2017

This blog post discusses the capabilities of SPI(Serial Peripheral Interface) in CYW43907.

CYW43907 contains two SPI interfaces:

 

1) SPI Flash Controller: a dedicated SPI flash controller which can support an external Quad SFlash.

2) CSC-Generic SPI: supports external SPI slave devices. In other words, it can only act as SPI Master.

 

The SPI Master is supported by the CSC(Cypress Serial Control) .There are two instances of SPI in CYW43907- SPI0 and SPI1

The SPI0 is referenced by WICED_SPI_1 (in WICED Studio) and SPI1 is referenced by WICED_SPI_2 in the platform file.(/43xxx_Wi-Fi/platforms/CYW943907AEVAL1F/platform.c).

 

SPI Controller supports a fixed SPI MODE : CPOL = 0, CPHA = 0 and 8 bit data read/write.

CPOL = 0: Clock idles at 0, leading edge is a rising edge, and the trailing edge is a falling edge

CPHA = 0: The “out”side changes the data on the trailing edge of the current clock cycle, the “in” side captures data on the leading edge of the clock cycle.

 

Following table shows the Pin name of SPI0 and SPI1.

WICED_SPI_1
MURATA Module Partner Pin Name
CYW943907AEVAL1F Pin Header
SPI0_CLKSPI_0_CLKJ6:12
SPI0_MOSISPI_0_MOSIJ6: 14
SPI0_MISOSPI_0_MISOJ6: 17
SPI0_CSSPI_0_CSJ6: 16

 

WICED_SPI_2MURATA Module Partner Pin NameCYW943907AEVAL1F Pin Header
SPI1_CLKSPI_1_CLKJ6: 9
SPI1_MOSISPI_1_MOSIJ6:13
SPI1_MISOSPI_1_MISOJ6: 11
SPI1_CSSPI_1_CSJ6: 15

 

Adding SPI to your application in WICED StudioThere are two drivers available in WICED Studio for CYW43907, Bit banging and CSC-GSIO driver. The bit-banging clock frequency is set as 1Mhz by default. To change it refer to the following blog:How to set SPI bit banging clock frequency in 4390X using WICED? For the GSIO driver, the minimum hold time requirement is 25ns. The bit-banging driver is CPU intensive and it is available for only the SPI0(WICED_SPI_1) interface.The drivers available for SPI0 could be selected in the platform file of CYW43907.(/43xxx_Wi-Fi/platforms/CYW943907AEVAL1F/platform.c).

 

 

Modify the SPI peripherals structure (platform_spi_peripherals) to select the driver. Following are the drivers available.

 

     a. spi_gsio_driver. ( default)

     b. spi_bb_driver.

 

 

API's available:

The SPI API’s are defined in /43xxx_Wi-Fi/WICED/platform/MCU/wiced_platform_common.c.

API documentation included as part of WICED Studio covers these APIs in great detail, here is a high-level description of APIs available for SPI for this device.

 

a. wiced_result_t wiced_spi_init( const wiced_spi_device_t* spi )

Description: This API can be used to initialize the SPI device. The structure wiced_spi_device_t initializes the SPI port, chip select pin, the SPI device speed, the mode of operation(see below for different modes), and the number of data bits.

An example of initializing wiced_spi_device_t  structure:

wiced_spi_device_t spi_device =

{

    .port               = WICED_SPI_1,

    .chip_select    = WICED_GPIO_22, //CS PIN IN 43097

    .speed            = 10000000,

    .mode             = ( SPI_CLOCK_RISING_EDGE | SPI_CLOCK_IDLE_LOW | SPI_MSB_FIRST ),

    .bits                 = 8

};

 

b.wiced_result_t wiced_spi_transfer( const wiced_spi_device_t* spi, const wiced_spi_message_segment_t* segments, uint16_t number_of_segments ):

Description: This is used to transmit/recieve the data. The initialized SPI device structure, along with message segment structure and the number of data segments are passed to this API. Each message could contain multiple data segments of the specified data width.(This width is initialized while defining the wiced_spi_device_t structure).

c.wiced_result_t wiced_spi_deinit( const wiced_spi_device_t* spi ) Deinitializes the spi interface.

 

Relevant Macros and Descriptions

WICED SPI Ports:

a) WICED_SPI_1 b) WICED_SPI_2

SPI mode constants and its descriptions:

SPI Mode FlagsDescription
SPI_CLOCK_RISING_EDGEData sampled at the Rising Edge
SPI_CLOCK_IDLE_LOWClock Idle State is Low
SPI_MSB_FIRSTData Transfer Direction with MSB first
SPI_LSB_FIRSTData Transfer Direction with LSB first
SPI_CS_ACTIVE_HIGHChip Select is Active High
SPI_CS_ACTIVE_LOWChip Select is Active Low

 

The attached application demonstrates setting up a SPI master in CYW43907 for communication with an external SPI slave. Follow the instructions added as comments in the code.

VinayakS_26

CYW43907 I2C Operation

Posted by VinayakS_26 Moderator Dec 8, 2017

This blog post discusses connecting CYW43907 to an I2C Slave. Cypress Serial Control (CSC) is an I2C compatible serial interface in CYW43907 and supports up to 400 KHz. CSC supports only I2C master that can be used to communicate with external I2C slaves. There are two instances of CSC blocks – I2C0 and I2C1.

 

I2C0 – This instance of I2C supports speeds such as  10 KHz, 100 KHz, and 400 KHz speed. I2C0 supports repeated start, however, it does not support clock stretching. Physical I2C0 pins are multiplexed with other functions(which could be found in the Pin Mux Table of CYW43907) and can be used as General Purpose I/Os(GPIO) if I2C0 is not being used by the application.

 

I2C1 – I2C1 also supports such as 10 KHz, 100 KHz, and 400 KHz speed. It does not support Repeated start and Clock stretching. I2C1 uses fixed function pins.

 

 

A bit banging I2C driver is also supported in WICED Studio that can be used for the applications that need to support clock stretching. Only I2C0 pins can be used for the bit-banging interface.

 

Pin List

The I2C pins are pulled up using 4.7K resistors in CYW943907AEVAL1F EVK.(as shown in the following figure).

 

I2C Interface
MURATA Module Pin Name
Pin Header
I2C0_SCLKI2C_0_SCLJ6. 23
I2C0_SDATAI2C_0_SDAJ6.25
I2C1_SCLKI2C_1_SCLJ12 .9
I2C1_SDATAI2C_1_SDAJ12.10

 

 

i2c_pullup.jpg

 

Adding I2C to your application in WICED Studio

Wiced Studio supports GSIO (CSC) based I2C or bit-banging. The I2C bit-banging driver is more CPU Intensive than the default hardware driver, so it is recommended to use I2C bit-banging only when the slave requires clock stretching. Note that I2C1 doesn't support bit-banging and hence the following options are applicable only for I2C0 interface.

The drivers available for I2C0 could be selected in the platform file of CYW43907.(/43xxx_Wi-Fi/platforms/CYW943907AEVAL1F/platform.c)

Modify the I2C peripherals structure (platform_i2c_peripherals)

  1. i2c_gsio_driver.(default)
  2. i2c_bb_driver.(bit-banging driver)

 

 

 

API’s available

 

In WICED Studio, physical I2C0 is referred as WICED_I2C_1 and I2C1 is referred as WICED_I2C_1 and must be used accordingly with APIs.

I2C API’s are defined in /43xxx_Wi-Fi/WICED/platform/MCU/wiced_platform_common.c.

API documentation included as part of WICED Studio covers these APIs in great detail, here is high-level description of APIs available for I2C for this device -


1.wiced_result_t wiced_i2c_init (const wiced_i2c_device_t * device)

Description: Initializes an I2C interface for communication as a master. The I2C port, speed modes, start address, addressing width along with the mode of operation (with or without DMA) for the interface is configured using this API. The API resets the I2C Pins to remove any previous states on the pins.

 

2.wiced_result_t wiced_i2c_write (const wiced_i2c_device_t* device, uint16_t flags, const void* buffer, uint16_t buffer_length )

Description: Writes data over the i2c interface. The start byte is (0000001) which pulls the SDA line low while the clock is high hence meeting the start condition. This is followed by the slave address. The data bytes are then transmitted to the slave. The stop condition is generated if the slave NACKs or the data transaction

completes through its entire length. The master sends a dummy byte before the stop condition is generated. It supports repeated start as well where the sender transfers multiple data bytes without sending the stop bit in between transfers. The Repeated start is supported only in I2C0 interface.

The flags that need to be passed to the API for generating the stop and start conditions respectively: WICED_I2C_STOP_FLAG, WICED_I2C_START_FLAG, WICED_I2C_REPEATED_START_FLAG

 

3.wiced_result_t wiced_i2c_read( const wiced_i2c_device_t* device, uint16_t flags, void* buffer, uint16_t buffer_length )

Description: Read data over an I2C interface from the slave corresponding to the slave address.  The transaction begins with a start byte from the master, followed by slave address. Data is read from the slave. This continues till the entire length of data is read or the slave NACKs. A dummy byte is sent by the master, before generating a stop condition. The flags that need to be passed to the API for generating the stop and start conditions respectively: WICED_I2C_STOP_FLAG, WICED_I2C_START_FLAG, WICED_I2C_REPEATED_START_FLAG.

 

4. wiced_result_t wiced_i2c_transfer( const wiced_i2c_device_t* device, wiced_i2c_message_t* messages, uint16_t number_of_messages )

Description: Used to do read/write data over an I2C interface. It supports repeated start condition where the sender transfers multiple data bytes without sending the stop bit in between transfers. The repeated start condition can only be generated in I2C0 interface.

 

5. wiced_bool_t wiced_i2c_probe_device( const wiced_i2c_device_t* device, int retries )

Description: Checks whether the device is available on a bus or not. This reads 2 bytes of data from the addressed slave. The slave won’t be acknowledged if it isn’t on the I2C Bus in which case the API returns 0.

 

 

Relevant Macros and Flags:

WICED Ports

(a) WICED_I2C_1(b) WICED_I2C_2

 

Addressing and Speed modes

Address width available for addressing the slave is set using the following enum flags.(For both GSIO and BB Drivers).

    I2C_ADDRESS_WIDTH_7BIT

    I2C_ADDRESS_WIDTH_10BIT

    I2C_ADDRESS_WIDTH_16BIT

 

Speed Modes available for the two drivers (Bit banging and GSIO) and the corresponding enum flags.

SPEED MODES
BIT BANGING
GSIO
I2C_LOW_SPEED_MODE5KHz10KHz
I2C_STANDARD_SPEED_MODE50KHz100KHz
I2C_HIGH_SPEED_MODE100KHz400KHz

 

The application attached reads the ADC output via an I2C interface and display in a webpage. Follow the instructions added as comments in the code.

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