• CY7C63813-SXC tray Package Carrier part#

    Have CY7C63813-SXC tray Package Carrier part#  for M/P? Regard,   Kevin
    KeTs_2342536
    last modified by KeTs_2342536
  • CY8C68013A 's issue of  Cypress FX2LP No EEPROM Device?

    hi   CYPRESS:     When i use  cypress  CY8C68013A to do myself tool, when i install the kit, it show Cypress FX2LP No EEPROM Device? in my sch , the iic connct to the at24c02 and sc...
    DaZh_2976111
    last modified by DaZh_2976111
  • cy7c65215 Jtag clock speed, is it fixed at 450KHz?

    We use openocd "adaper_khz" to set cy7c65215's jtag clock speed. But the command takes no effect, though openocd doesn't report errors. Measuring the jtag clock with oscilloscope, it is always 450khz. Can we change it...
    YuCh_4287461
    last modified by YuCh_4287461
  • CY7C68013A-56PVXC create a hex dump

    Hello everyone,   I have question. Is there any way I can create a CY7C68013A-56PVXC hex dump and how can I create one?What is needed? Also make from the copy hex dump and upload it to another same chip. Hoop so...
    CrKl_4346426
    last modified by CrKl_4346426
  • Windows 10 Enterprise 2019 LTSC Driver for CY7C65213

    Hello,   I think that Windows 10 Driver for CY7C65213 (USB-UART LP Bridge Controlle) can be downloaded as follows.   http://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-developmen...
    HaSh_1328096
    last modified by HaSh_1328096
  • EZ-USB FX2 iic file not generated(FX3_SDK)

    When FX2 device with FX3 SDK , .hex file is generated but iic file is not generated. I can write program to RAM but can't write to EEPROM because there is no iic file.   Files built with keil can be converted t...
    hata_3396041
    last modified by hata_3396041
  • CY8C68013A  date send issue?

    hi  Cypress:      在使用CY8C68013A的问题,上位机需要发送512Byte 或者其整数倍的数据才能接受到; 如果发小于512Byte 的数据 则无法接受到, USB的相关协议中应该是需要发送相关操作指令才可以实现非512byte 接受, 客户需要知道怎么进行操作? 是否有相关的 建议; TKS;
    DaZh_2976111
    last modified by DaZh_2976111
  • How to disarm previously armed in endpoint1 of FX2LP?

    How to disarm previously armed in EP1IN?
    MoTa_938296
    last modified by MoTa_938296
  • EZUSB Part Selection for USB 2.0 UVC Camera MJPEG Support

    Hi I am interested in using the EZ USB chips for a new design and would like some help choosing the best part that has software example to prove concept. These are the requirements:   - USB 2.0 device (USB 3.0 no...
    SeSc_4288176
    last modified by SeSc_4288176
  • fx2lp isochronous aadj with 512 quad buffering and 2 additional transactions per microframe

    Probably answering the question myself, the TRM states that the aadj=1 will check only 1024byte commited buffers but I was wondering if it should work also on 512byte packets /fifo buffers for IN(2) endpoints. It does...
    HSo_3703166
    last modified by HSo_3703166
  • The  date send of  CY7C68013A-56LTXC?

    hi   Cypress:        The problem with cy7c68013a-56ltxc is that the host computer needs to send 512Byte or integer multiple data to receive it. If the data sent is less than 51...
    DaZh_2976111
    last modified by DaZh_2976111
  • More information about driver reselling process

    Hello, We designed a device that uses Cypress CY7C68013 chip in order to initiate USB2 high speed communication (30MB/s throughput). We want our users to be able to use the device with Windows 10 64 bit and 32 bit o...
    AvAh_1250071
    last modified by AvAh_1250071
  • FX2LP EP1IN problem

    I assume that SIE of FX2LP responds immediately to EP1IN bulk transaction without NACK one or two times soon after "SET_FEATURE(to endpoint81) REQUEST" although firmware does not arm the EP1IN yet. EP1IN is armed in ...
    MoTa_938296
    last modified by MoTa_938296
  • FIFO Slave / GPIF interface clock direction

    Hello,   I am considering using FX3 as a bridge between USB and FPGA. It would be mainly used to pass data from USB to application via FX3 at maximum BW (low traffic in other direction). My project is at bo...
    chroc_4339966
    last modified by chroc_4339966
  • cy7c65215 jtag pin types and connections

    What modes are cy7c65215 jtag's output pins: Open-drain or push-pull? Are they configurable? Also, should we have a pull-up resistor for TDO (jtag master's input pin)?   SCB1 pins: TDO    &...
    YuCh_4287461
    last modified by YuCh_4287461
  • Low Cost Hardware USB Packet Sniffer using CY68013A

    We built a hardware packet sniffer as an add-on for the FX2LP boards that are sold on ebay, AliExpress and similar sites.   I can answer technical questions here. Other info is on www.bugblat.com/products/ezsniff/
    tiecc_1833756
    created by tiecc_1833756
  • VID_04B4&PID_CC04 drivers

    Hello,   I work as a computer technician for a french hospital and I'm searching for a driver. After HDD crash, I reinstalled a computer who is connected to an obscure medical peripheral. I couldn't find any ...
    PiNI_4336196
    last modified by PiNI_4336196
  • Hard reset Vs Soft reset

    Hi Service desk,   1) What are the functional differences between issuing hard reset to RESET_N pin Vs soft reset using USB->Reset(). 2) Also, How to apply "CPU only Reset" or "Whole device reset" using the...
    trsoc_3997646
    last modified by trsoc_3997646
  • identifying more than one CY7C65211 in Windows' USB tree (Windows Device ID)

    I have designed a new product that uses the CY7C65211 USB-Serial interface.  Some users will connect more than one of my products to their computer, so I need to identify the Windows Device ID of each of the CY7C...
    dacuc_1521966
    last modified by dacuc_1521966
  • step by step procedure to program CY68013A device as Slave FIFO FPGA as Master

    hello, I need to get data from FPGA (vetex -5 , XC5VLX110) to PC.  I am Using Keil for creating .hex file . I want to know how to program CY68013A and How to get data from FPGA ...I am new to this process. Initia...
    PaKu_3818476
    last modified by PaKu_3818476