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CYPD3177(BCR) has provided four sets of resistor divider networks are used to determine the voltage and current range that the EZ-PD BCR device will negotiate

with the USB Type-C power adapter. However, if it still cannot meet your requirement, you can change the PDO through its I2C register.


This blog gives a breif introduction on how to change the BCR register based on BCR HPI Spec.

1. Hardware Connection

Figure 1

Connect SCLK and SDAT of MiniProg to CY4533 as is shown in Figure 1. Set the rotary switch (SW1) to position 1 so CY4533 support 5V/0.9A by default. Use a CY4500 EZ-PD Protocol Analyzer to capture the cc communication between CY4533 and the power adapter.


Figure 2

As is shown in Figure 2, CY4533 request 5V/0.9A due to the max requesting VBUS set by rotary switch is 5V/0.9A.

2. Send I2C command in Bridge Control Panel to control BCR

Figure 3

Check the PD_STATUS register first. The value of PD_STATUS register is 00 A4 05 00. It means the explicit contract has been established between BCR and the charger. BCR is acting as a power sink and the two device both supports PD 3.0. To replace the default sink PDO, write the corresponding packet into the data memory start from 0x1800. For Byte 0-3, ASCII string “SNKP” (i.e 0x50 0x4B 0x4E 0x53) must be sent to make BCR update its sink PDO list. In this example, PDO 0 is set to 5V/0.9A and PDO 1 is set to 15V/1.75A. The remaining bytes are set to 0 because not all 7 PDOs are used.  Refer to Section 6.4 of Universal Serial Bus Power Delivery Specification for the description of Fixed Supply PDO. Figure 3 is the I2C commands sent and response from BCR.

Figure 4

After enabling the PDO0 and PDO1 mask by sending command to SELECT_SINK_PDO register, BCR will re-negotiate the PD contract with the power adapter. PD_RESPONSE register should be checked after sending command on command registers. 0x02 is the code for successful operation.CC communication is captured by CY4500 in Figure 4.



Post_build Script Failure

Posted by YiZ_31 Moderator Aug 13, 2019

When using PSoC Creator compiling a new project generated from CCGx Host SDK, you could meet such error:


"Post-Build Script failed: Primary and backup binaries are overlapping."

The command '.\post_build.bat' failed with exit code '1'.

--------------- Rebuild Failed: 08/13/2019 15:50:15 ---------------


There are two ways to avoid this problem.

  • Creating Project from Start Page

The SDK example projects are listed underKits -> EZ PD CCG CCGx Host SDK on the Start Page. Click on the workspace name to copy it. When copying the workspace, the complete workspace directory along with all the projects associated with the workspace are copied to the selected destination location. PSoC Creator automatically opens the copied workspace after completing the copy.

In this way, the Post-Build Script failure problem could be avoided, but the project name could not be changed.

  • Creating Project from Code Examples
  1. Use File->New->Project to create a new project. Modify the workspace name and project name to whatever you want.
  2. Right click on workspace name and use Add a Existing Project to add backup_fw.cyprj to the workspace.
  3. Right-click on workspace name and use Dependencies to add a code dependency for the CYPD3125-40LQXI_notebook project on the backup_fw project.

    4. Edit the post_build.bat script file in the project folder. Change CYPD3125-40LQXI_notebook in @set "PROJ=CYPD3125-40LQXI_notebook" to your project name.

Below steps for make a firmware for CCG3PA Power Adapter/Car Charger (1C+1A) single chip solution based on example firmware CYPD3171-24LQXQ_cla.


1. New created a project based on firmware source code CYPD3171-24LQXQ_cla.

a. Click File > New > Project, and select Ez-PD CCGx Power SDK (CCG3PA) as Target kit.

b. Select Code Example:CYPD3171-24LQXQ_cla.

c. Create a new work-space and choose a name and location for the design. (Since the target part number is going to use CYPD3175, so that I named it start with CYPD3175.)

NOW, the new project is created complete.


2. Clean the project as per CY4532 hardware schematic before start your new project if the hardware is not totally same as CY4532.

a. Change the part number of cc bootloader.

(1) Add a cc bootloader project into the workspace. (There are two types of cc bootloader, cc_sink_boot.cydsn and cc_src_boot.cydsn. cc_sink_boot.cydsn will present as power sink role with this bootloader after entering boot mode. cc_src_boot.cydsn will present as power source role with this bootloader after entering boot mode. )

(2) Change the part number of cc bootloader to make sure the bootloader project and application project use same project.

(3) Re-build cc bootloader project and update Bootloadable dependencies HEX and ELF files.

b. Clean application project.

(1) Type-C Port

Disable BUCK_BOOST_EN_C on TopDesign.cysch. Comment out or delete relates functions/operation of BUCK_BOOST_EN_C.

(2) Type-A Port

Disable PWM_A, BUCK_BOOST_EN_A, and TYPE_A_VBUS_EN. And open type_a.c and config.h files for cleaning firmware.

@file type_a.c.

Comment out line#55 - line#62

clear functions:

void type_a_enable_sdp(void)

static void type_a_enable_boost(void)

static void type_a_disable_boost(void)

void type_a_reg_switch_timer_cb(uint8_t instance, timer_id_t id)

void type_a_set_volt_timer_cbk(uint8_t port, timer_id_t id)

void type_a_set_voltage(uint16_t volt_mV)


@file config.h


@file stack_prarams.h

/* Dual regulator support for TYPE-A VBUS. */

//1C+1A #define TYPE_A_DUAL_REG_ENABLE                  (1u)


NOW, the firmware project is cleared. The project can verified on the board with Type-C port directly.


3. Add functions as per application.

a. Add a I2C Master/Slave in CCG3PA.

b. Use GPIO for Type-A VBUS current sense. Below function is example for using P2.3 for Type-A current sensing.


uint16_t Read_PortA_Current(void)


    uint8_t level;

    uint16_t current_volt;


    /* Configure GPIO. */

    hsiom_set_config(GPIO_PORT_2_PIN_3, HSIOM_MODE_AMUXA);

    /* Take ADC sample. */

    level = pd_adc_sample (0, PD_ADC_ID_1, PD_ADC_INPUT_AMUX_A);

    current_volt = pd_adc_level_to_volt (0, PD_ADC_ID_1, level);


    hsiom_set_config(GPIO_PORT_2_PIN_3, HSIOM_MODE_GPIO);


    return current_volt;



c. Add state machine for Type-A and Type-C power source capabilities. Below APIs can be refer to mask Type-C or Type-A power source capabilities.



* @brief This function updates the source PDOs at runtime thereby overriding

* the source PDOs in the config table.

* @param port Port index.

* @param count Count of PDOs.

* @param pdo Pointer to the PDO array.

* @return CCG_STAT_SUCCESS if operation is successful, CCG_STAT_BAD_PARAM

* otherwise.


ccg_status_t dpm_update_src_cap(uint8_t port, uint8_t count, pd_do_t* pdo);




* @brief This function updates the source PDO mask at runtime thereby

* overriding the source PDO mask in the config table.

* @param port Port index.

* @param mask PDO mask.

* @return CCG_STAT_SUCCESS if operation is successful, CCG_STAT_BAD_PARAM

* otherwise.


ccg_status_t dpm_update_src_cap_mask(uint8_t port, uint8_t mask);



* @brief This function updates the battery charging configuration.

* This is valid only if LEGACY_DYN_CFG_ENABLE macro is enabled. The configuration

* can only be updated when the BC state machine is stopped. Also note that

* bc_init() shall reload the configuration from the table.


* @param cport Battery Charging port index.

* @param chg_cfg Pointer to structure containing new configuration.


* @return ccg_status_t


ccg_status_t bc_set_config(uint8_t cport, chg_cfg_params_t *chg_cfg);

CCG3PA Power Adapter/Car Charger reference design in Type-C reference designs (LINK: ) is below structure as per the reference design name and link.


1. CCG3PA Car Charger Reference Design using Southchip ( )

The hardware block diagram is below:

2. EZ-PD™ CCG3PA USB-C PPS 39W Dual Port Car Charger (Power Adapter) Reference Design (

The hardware block diagram is below:

3. EZ-PD™ CCG3PA USB-C Mobile Power Adapter Solution using Power Integrations ( )

The hardware block diagram is below:

4. EZ-PD™ CCG3PA USB-C Mobile Power Adapter Solution using Diodes ( )

The hardware block diagram is below:

5. 45W EZ-PD™ CCG3PA USB-C Notebook Power Adapter Solution using MPS ( )

The hardware block diagram is below:

From all of block diagram, the design is demonstrating each port (either Type-C or Type-C) have dedicated DC/DC convector or AC/DC convector. If you are looking for a single DC/DC convector or AC/DC convector designed to service Type-C and Type-C port. Below block diagram could be refer to. This design could be easy to achieve based on above reference design.


1) VBUS_IN_DIS and VBUS_C_MON can be exchanged.

2) The VBUS enable sequence is supported by dynamically, the priority of Type-C or Type-A shall be defined before firmware customize. (This is trade off the BOM cost down).

3) Need additional Type-A detach/attach circuits for Type-A port. If the detach/attach circuits is composed by Amplifier, the current detect accuracy shall be consideration (50mA as minimum recommend).

4) CCG3PA is looking for Vfb=1.2V.

Take CYPD3125 for example. Here are the steps to change it to CYPD3123:

1.Right click on Project ‘CYPD-3125-40LQXI_notebook01’ [CYPD-3125-40LQXIT] and choose Device Selector…

Change the part number from CYPD3125-40LQXIT to CYPD3123-40LQXIT

2. TopDesign.cysch page, double click on Bootloadable_1 component. Click on Dependencies tab and change the path of Bootloader HEX file. The bootloader file of CYPD3123-40LQXIT can be found in “C:\Program Files (x86)\Cypress\EZ-PD CCGx SDK\CCG3-CCG4\Firmware\projects\CYPD3123-40LQXI_ctd_us\CYPD3123-40LQXI_ctd_us.cydsn\Bootloader”. The Bootloader ELF file path will be changed automatically when Bootloader HEX file path has been modified.

3.Compile the project.


The project still uses the USB bootloader of the CYPD3123. If you want a CYPD3123 project with I2C bootloader, then you’ll need project file for the bootloader of CYPD3125 (which is not included in the current version of SDK). Change the device part number with the same steps above, then use the generated HEX file for bootloader dependency.

CYPD2122 notebook firmware is default programming firmware of CY4521 and it is support 5V source PDO only. If you need CY4521 to evaluate additional PDOs higher than 5V, the process is below.


Hardware setup based on CY4521 board Rev.03 default setting.


OPEN J11 1-2; (GPIO for LED blink)

SHORT TP17 and TP20; (Equal to load R22); (VSEL1 for DC/DC feedback control)

SHORT TP18 and TP21; (Equal to load R23); (VSEL2 for DC/DC feedback control)


Firmware changes as below:

1) Add additional source PDOs 9V/5A, 15V/5A, and 20V/3A with Ez-PD configuration Utility. And then update config table in CYPD2122 firmware config.c file.


2) Update bootloader hex file in bootloadable components.

3) Open TopDesign.cysch, disable LED_PIN and I2C_CONFIG (Please notice only disble I2C config on application not on the I2C bootloader.). Add new output pins and named VSEL1 and VSEL2.

4) Open notebook.cydwr. add pin assignment of VSEL1 to P1[1] and VSEL2 to P1[2].


5) Comments out below lines to enable VSEL1 and VSEL2 function and voltage macro define (based on SDK v3.0.2).

a. @psource.h

- (line 86, col 1): // #ifdef PD_APP_POWER_ADAPTER_INC

- (line 95, col 1): // #endif /* PD_APP_POWER_ADAPTER_INC */


b. @psource.c

- (line 140, col 1): // #ifdef PD_APP_POWER_ADAPTER_INC

- (line 256, col 1): // #endif /*PD_APP_POWER_ADAPTER_INC*/

- (line 478, col 1): // #ifdef PD_APP_POWER_ADAPTER_INC   

- (line 481, col 1): // #endif /* PD_APP_POWER_ADAPTER_INC */   

- (line 505, col 1): // #ifdef PD_APP_POWER_ADAPTER_INC

- (line 509, col 1): // #endif /* PD_APP_POWER_ADAPTER_INC */


6) Rebuild firmware to generate hex file for CY4521.


The CY4532 power bank design is support Type-C and Type-A.

Type-C is Dual Role Power (Source Role: Type-C: 5V/3A, 9V/2A; Type-A: BC1.2, QC3.0, AFC (5V/3A, 9V/2.1A, and 12V/1.05A. Sink Role: Type-C: 5V/3A; Type-A: BC1.2 and Apple Charging.).

Type-A is Power Source Role only (BC1.2, QC3.0, AFC (5V/3A, 9V/2.1A, and 12V/1.05A. ).


1. SC8802 is DC/DC for Type-C VBUS power source and sink DC/DC buck-boost regulator.

CCG3PA control pins:

Pin#1 PWMI_OUT_C :Current setting for SC8802.

Pin#2 BUCK_BOOST_EN_C :Enable SC8802.

Pin#9 DIR_CTRL_C :Charging and Discharging direction control for SC8802.


2. SC8701 is DC/DC for Type-A VBUS power source.

CCG3PA control pins:





3. Type-A VBUS current sense on VBUS high end via INA199A3DCKR. The target is for Type-A device disconnection detected. It is wired to pin#13 of CCG3PA.


Based on above design, in order to get a clear SDK which is not related to any DC/DC, it shall be remove all of above firmware code to make it happen.




1. Clear @file config.h


* PSOURCE controls for PD port 1.


#define APP_VBUS_SRC_FET_ON_P1()                    pd_internal_cfet_on(0, false)


#define APP_VBUS_SET_VOLT_P1(volt_mV)               vbus_ctrl_fb_set_volt(TYPEC_PORT_0_IDX, volt_mV)


#define APP_VBUS_SRC_FET_OFF_P1()                   pd_internal_cfet_off(0, false)



* PSOURCE controls for Port 2 (TYPE A port).


#define APP_VBUS_SRC_FET_ON_P2()                    vbus_ctrl_pwm_turn_on(TYPEC_PORT_1_IDX)


#define APP_VBUS_SET_VOLT_P2(volt_mV)               vbus_ctrl_pwm_set_volt(TYPEC_PORT_1_IDX, volt_mV)


#define APP_VBUS_SRC_FET_OFF_P2()                   vbus_ctrl_pwm_turn_off(TYPEC_PORT_1_IDX)



* Power Sink (PSINK) controls for PD port 1.


/* Function/Macro to turn consumer FET for P1 ON. */

/* Enable consumer direction, turn on Consumer FETs and enable Buck Boost converter. */

#define APP_VBUS_SNK_FET_ON_P1()                    pd_internal_cfet_on(0, false)


/* Function/Macro to turn consumer FET for P1 OFF. */


* Disbale Buck Boost converter, turn off Consumer FETs, set direction to provider mode

* and turn off PWM I which limits current consumption.


#define APP_VBUS_SNK_FET_OFF_P1()                   pd_internal_cfet_off(0, false)


2. @ file power_bank.c

line#49: comment out #define VBATT_MON_GPIO                         (GPIO_PORT_2_PIN_1)


line#64 - line#94 : Comment out all of contents in function void pb_typec_set_current (uint16_t cur_10mA)


line#151 -line#165: Comment out all of contents in function static uint16_t pb_get_battery_voltage(void) to fake battery voltage check (Return a constant value with 4.2V to let power bank state machine tuning well.)


3. @ file power_bank.h

line#51 - line#59 Comment out all of MACRO defines for PWM control.




There are two dongle reference design based on CCG3:

Type-C plug to DisplayPort:

Type-C plug to HDMI/VGA/DVI:

Charge-Through Dongle (equal to Type-C plug to USB3.0/HDMI/Type-C (charge only)) :


If you are going to merge a single Type-C port (Receptacle) into your USB3.0/DisplayPort/HDMI input device. The Type-C plug is not nice to show up on your products. This blog is recommended to take a look.


Below content is schematic explain Type-C receptacle DRP Reference Design (Power source & DisplayPort Sink and USB 2.0 host role <Need wire DP/DM to USB2.0 host.>).

1. Block Diagram:

2. In Details:

a. Part number can suit for this design (Since USB bootloader firmware project is not applied to all of CCG3 device, this design cannot apply to all of devices of CCG3 to save bootloader customize efforts.):

b. PS8742B can be replace with others same function DE MUX (Support DisplayPort Sink at least). CCG3 support I2C/PWM/GPIO control. This design use I2C control (CCG3 is I2C master).


c. DP_Indicator is used for inform DisplayPort/HDMI sink control system that DP ALT Mode is entered and DisplayPort signals is coming.


d. USB2.0 Switch wire to CCG3 internal billboard by default. If attached USB2.0 Device and sink on Type-C receptacle, USB2.0 switch will switch to USB2.0 host in the system.

Cypress SDK firmware demonstrate below feature in difference SDK firmware (@ December, 2018).

1. CCGx Host SDK (…  )

>> Power Source and Sink Role;

>> DisplayPort Source Role with Alternate Mode.


2. CCGx Power SDK (… )

>> Power Source and Sink Role;


3. CCGx Dock SDK (  )

>> Power Source and Sink Role;

>> DisplayPort Sink Role with Alternate Mode.


If you want to change DisplayPort Role based on above #1 and #3, either DisplayPort Source to DisplayPort Sink or DisplayPort Sink to DisplayPort Source. Only need take attention on below define to make sure below defines have been configured as per design requirements.


For Example: DisplayPort Source based Projects change to DisplayPort Sink.

@file: config.h


/* Enable Alternate Mode support when CCG is DFP. */

#define DFP_ALT_MODE_SUPP                           (0u)



/* Enable DisplayPort Source support as DFP. */

#define DP_DFP_SUPP                                 (0u)



/* Enable Alternate mode support as UFP. */

#define UFP_ALT_MODE_SUPP                           (1u)



/* Enable DP Alternate mode support in UFP mode. */

#define DP_UFP_SUPP                                 (1u)


@file: alt_modes_config.h


#define DFP_MAX_SVID_SUPP                       (0u)



#define UFP_MAX_SVID_SUPP                       (1u)


#define MAX_SVID_SUPP                           (DFP_MAX_SVID_SUPP > UFP_MAX_SVID_SUPP ? \

                                                        DFP_MAX_SVID_SUPP : UFP_MAX_SVID_SUPP)


@Software: EZ-PD configuration Utility

a. Open Ez-PD configuration Utilities to add SVID of DisplayPort Sink.

b. Select SVID Configuration and click +Add, SVID 0 will be add under SVID Configuration.

c. Select SVID 0 and edit SVID value and Mode on the right page. Change SVID value 0x0000 (default) to 0xFF01, Mode 0 value from 0x0 to 0x00001405(Plug design)/0x00040045(receptacle design).

d. Click File>Save As.

e. Find the .c file under the folder you have been saved on step c) above.

f. Open config.c under Source files in project. Change config table const unsigned char __attribute__ ((section (".configSection"), used)) gl_config_table[0x0400] by replace the table value from the .c file from Ez-PD configure Utilities above.


Otherwise, DisplayPort Sink change to DisplayPort Source is revise above ENABLE and DISABLE items.

1. New created CCGx project based on example code. (Use CCGx Host SDK, since the CCGx project in the Host SDK have includes i2c-boot project.)

  • File >> New >> Project…
  • Select project type >> Target kit: EZ-PD CCGx HOST SDK (CCG3)

  • Select project template >> Code example


  • Select a code example >> CYPD3125-40LQXI_notebook


  • Create Project>> name workspace/specify location/name project name.

  • Add i2c_boot project into workspace: right click “Workspace”, select Add>> Existing Project…


2. Boot-loader Project Changes.

  • Open TopDesign.cysch of i2-boot project. And then double click Bootloader_1 component to Make sure that the “Dual-application bootloader” option is unchecked.

  • Open config.h file from i2c-boot project head files. Enable define CCG_DUALAPP_DISABLE (CCG_DUALAPP_DISABLE is set as 0u for dual images by default.)

  • Compile the project to generate the customized single bootloader binary (.hex & .elf).


3. Application Project Changes (notebook example).

  • Pre-build CYPD3125-40LQXI_notebook. cyprj project and generate all relates files.
  • Open the CYPD3125-40LQXI_notebook. cyprj project using PSoC Creator 4.2 (the latest version). Double click Bootloadable_1 component and updates the. hex file and .elf file from above process.

  • Update Project -> Build Settings -> Debug -> Debug Target from Application Code and Data 2 to Application Code and Data.

  • Update linker script for single image build.

  • Open the “Project -> Build Settings -> ARM GCC -> User Commands” section and add the following pre-build command.

cmd /c "copy .\Bootloader\CYPD3125-40LQXI_i2c_boot_1_0_3_461_0_0_0_nb.c Generated_Source\PSoC4\cybootloader.c & copy .\Bootloader\CYPD3125-40LQXI_i2c_boot_1_0_3_461_0_0_0_nb.icf Generated_Source\PSoC4\cybootloader.icf"

-----------------------------------------Make sure first step was completed----------------------------------------------

  • Build All project


-- Attach files:

1. Guide.pdf -- steps for Create a single firmware build based on CCGx Host SDK v3.2.1 example project PDF format.

2. -- Example project based on CYPD3125-40LQXI_notebook.

3. cm0gcc.ld -- link script for single image.

Below errors may be met if you are using the new CCG5 example project under CCGx HOST SDK (…  ).


1. Forgot to pre-build backup_fw.

>> After click File >> New >>Project Projectmenu option also allows you to create a new project based on existing example projects. Please kindly Add backup_fw from the project folder you have been pointed to when you new created a project with PSoC Creator.

2. Meet one ERROR caused by PSoC Creator 4.2 (C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin) is not be added into system environment path.  ('cyelftool.exe' is not recognized as an internal command, operable program or batch file.)

3. Meet one ERROR caused by post_build.bat Project name is not changed as per new project name if NEW project name is not CYPD5225-96BZXI_notebook or CYPD5125-40LQXI_notebook. (CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf: Failed to open CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf)

>> Kindly OPEN post_build.bat and edit it

This Blog documents how to port DRP USB3.0 and DisplayPort 4 lane and remove CTD US functions from Charge Through Dongle (CTD) upstream project. Original example project can be get it from CCGx SDK V3.0.2. LINK:… 


1. Disable I2C Master +HPI INT. The original code (CTD) uses I2C Master interface for HPI with CTD DS.

2. Disable USB-I2C master bridge mode support @file config.h.

/* Enable USB-I2C master bridge mode support. */

#define APP_I2CM_BRIDGE_ENABLE                      (0u) //CTD clear 1->0


3. Comment out all of function related CTD DS. I used Marco define DISABLE_CTD_US and add it into file config.h.

@file main.c

Comment out all of functions which is named begin with "ctd_". And register Application callback functions for the DPM without "ctd_".

Clear content of function void sln_pd_event_handler(uint8_t port, app_evt_t evt, const void *data)


@file ctd_us_solution.c

Comments all functions. Recommend to add #ifndef DISABLE_CTD_US //Clear CTD after all of #include @ file ctd_us_solution.c.


4. Example project attached with Blog. What's I was customized can be found with "DISABLE_CTD_US".

CCG3 SDK notebook firmware example project is Dual Role Power (Power source and Power sink) and support Data source (DisplayPort source or USB3.x data host). It is regards as hardware of CY4531 board.

a. SDK firmware download link:…

b. CY4531 download link:


CCG3 have Integrated Hardware based over-current protection (OCP), related pin is pin#39 OC Over-current Sensor Input. The standard circuits recommended to realize OCP can be refer below (highlight with red box).


You are correct that this is only on Provider path. Which meant the firmware is following the hardware design, the OCP only on Power source role. If you are designing a power sink with CCG3 and could like to implement OCP on consumer path. This is the right place to take a look.


Copy functions with power source role and update OCP features in sink role. (The OCP on power source role is disabled, since this is UFP target.)

Hardware end, you need Rsense 10mOhm on power consumer path same as above. (Change the Rsense from power Provider path to power Sink path).  


Firmware end, you can re-use the function which is using in VBUS_OCP on power source role. Below example functions your may need to be refer to.

a. Add Function declarations for OCP at file psink.c.


static void psnk_dis_ocp(uint8_t port);

static void psnk_shutdown(uint8_t port, bool discharge_dis);

void app_psnk_vbus_ocp_cbk(uint8_t port);


b. Add Type-C current level as per Type-C SPEC.


/* Type-C current levels in 10mA units. */

#define CUR_LEVEL_3A    300

#define CUR_LEVEL_1_5A  150

#define CUR_LEVEL_DEF   90


static const uint32_t cc_rp_to_cur_map[] = {






c. Update psnk_enable function. Example as below with VBUS_OCP_ENABLE


void psnk_enable (uint8_t port)


    uint8_t intr_state;



    uint32_t ocp_cur;


    const dpm_status_t *dpm_stat = dpm_get_info(port);

    intr_state = CyEnterCriticalSection();


    if (dpm_get_info(port)->dpm_enabled)



            if (get_pd_port_config(port)->protect_en & CFG_TABLE_OCP_EN_MASK)


                if (dpm_stat->pd_connected)


                    ocp_cur = dpm_stat->snk_cur_level;




                    ocp_cur = cc_rp_to_cur_map[dpm_stat->snk_cur_level];



system_vbus_ocp_en(port, ocp_cur, app_psnk_vbus_ocp_cbk);


    #endif /* VBUS_OCP_ENABLE */       






d. Add a new function for power sink ocp call back.



void app_psnk_vbus_ocp_cbk(uint8_t port)


    /* OCP fault. */

    /* Quickly turning off fets here, although dpm_stop will also do that. */

    psnk_shutdown(port, true);

    /* Stopping dpm before sending app event. If OCP retry logic is enabled, app will

     * restart the dpm. */


    /* Enqueue HPI OVP fault event. */

    app_event_handler(port, APP_EVT_VBUS_OCP_FAULT, NULL);



#endif /* VBUS_OCP_ENABLE */


e. Add a new function for power sink OCP disable.


static void psnk_dis_ocp(uint8_t port)



    if (get_pd_port_config(port)->protect_en & CFG_TABLE_OCP_EN_MASK)




#endif /* VBUS_OCP_ENABLE */



f. Add disable OCP when power sink is shut down. Example as below with VBUS_OCP_ENABLE



static void psnk_shutdown(uint8_t port, bool discharge_dis)


    /*Turn Off Source FET*/



    if(discharge_dis == true)





    /* Disable OVP/OCP */

app_ovp_disable (port, false);



#endif /* VBUS_OCP_ENABLE */





This is place to share CCGx footprint for Cadence. (continue to update regarding CCGx update)

1. CCG1 (35-WLCSP, 40-QFN, 16-SOIC)

2. CCG2 (20_CSP, 14-DFN, 24-QFN)

3. CCG4 (40-QFN, 24-QFN)

4. CCG3 (40-QFN,42-CSP, 32-QFN)

5. CCG3PA (24-QFN, 16-SOIC)

6. CCG5 (96_BGA, 40_QFN)


Each package will update only once, the same package can apply same footprint for difference part number.

1. [CCG2 is power sink role] Adjust request PDO as per SOURCE CAP advertised.


{CCG2 firmware is following PD 2.0 SPEC, the function static bool is_src_acceptable_snk(tPD_DO* pdo_src, tPD_DO* pdo_snk) @ file cy_solution.c is for checking which sink PDO is acceptable based on the SOURC_CAP from DFP. CCG2 firmware is select out the one match the SOURCE_CAP as per Power Delivery SPEC, which is means, the sink voltage and current shall be covered by SOURCE_CAP (Voltage shall be match, Current of SOUCE CAP s larger or equal sink capabilities), otherwise, CCG2 will request 5V request.}

>> Need update the case PDO_FIXED_SUPPLY. Example is below


                    if(fix_volt == pdo_snk->fixed_snk.voltage)


                        max_type_cur = get_max_cur(0u, pdo_snk, fix_volt);

                        if(pdo_src->fixed_src.max_current >= max_type_cur)


                            contract_power = udiv_round_up(fix_volt * pdo_snk->fixed_snk.op_current, 500u);

                            contract_voltage = fix_volt;

                            op_cur_power = pdo_snk->fixed_snk.op_current;

                            out = true;


                        //Added for update current for mismatch current only

                        else if(fix_volt > V_SAFE_5V)


                            contract_power = udiv_round_up(fix_volt * pdo_src->fixed_src.max_current, 500u);

                            contract_voltage = fix_volt;

                            op_cur_power = pdo_src->fixed_src.max_current;

                            max_type_cur = pdo_src->fixed_src.max_current;

                            out = true;





2. [CCG2 is power sink role] Request DR_SWAP or PR_SWAP


{Type-C SPEC defines Power source role as data host by default and power sink role as data device. Type-C can support Power role is not sync with data role. For example, Power source role and data sink role.}

>> Firmware implement process is: (PR_SWAP for example, and expect to work as Power source role.)

a. Check current role.((get_current_port_role() == PRT_ROLE_SINK) )

{There may need add more conditions to go ahead to next step, for example, make sure power source is already asserted.}

b. send PR_SWAP if the current role is not match the expect. (handle_pd_command (DPM_CMD_PR_SWAP, NULL, NULL); )



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