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The CY4532 power bank design is support Type-C and Type-A.

Type-C is Dual Role Power (Source Role: Type-C: 5V/3A, 9V/2A; Type-A: BC1.2, QC3.0, AFC (5V/3A, 9V/2.1A, and 12V/1.05A. Sink Role: Type-C: 5V/3A; Type-A: BC1.2 and Apple Charging.).

Type-A is Power Source Role only (BC1.2, QC3.0, AFC (5V/3A, 9V/2.1A, and 12V/1.05A. ).



1. SC8802 is DC/DC for Type-C VBUS power source and sink DC/DC buck-boost regulator.

CCG3PA control pins:

Pin#1 PWMI_OUT_C :Current setting for SC8802.

Pin#2 BUCK_BOOST_EN_C :Enable SC8802.

Pin#9 DIR_CTRL_C :Charging and Discharging direction control for SC8802.


2. SC8701 is DC/DC for Type-A VBUS power source.

CCG3PA control pins:





3. Type-A VBUS current sense on VBUS high end via INA199A3DCKR. The target is for Type-A device disconnection detected. It is wired to pin#13 of CCG3PA.


Based on above design, in order to get a clear SDK which is not related to any DC/DC, it shall be remove all of above firmware code to make it happen.




1. Clear @file config.h


* PSOURCE controls for PD port 1.


#define APP_VBUS_SRC_FET_ON_P1()                    pd_internal_cfet_on(0, false)


#define APP_VBUS_SET_VOLT_P1(volt_mV)               vbus_ctrl_fb_set_volt(TYPEC_PORT_0_IDX, volt_mV)


#define APP_VBUS_SRC_FET_OFF_P1()                   pd_internal_cfet_off(0, false)



* PSOURCE controls for Port 2 (TYPE A port).


#define APP_VBUS_SRC_FET_ON_P2()                    vbus_ctrl_pwm_turn_on(TYPEC_PORT_1_IDX)


#define APP_VBUS_SET_VOLT_P2(volt_mV)               vbus_ctrl_pwm_set_volt(TYPEC_PORT_1_IDX, volt_mV)


#define APP_VBUS_SRC_FET_OFF_P2()                   vbus_ctrl_pwm_turn_off(TYPEC_PORT_1_IDX)



* Power Sink (PSINK) controls for PD port 1.


/* Function/Macro to turn consumer FET for P1 ON. */

/* Enable consumer direction, turn on Consumer FETs and enable Buck Boost converter. */

#define APP_VBUS_SNK_FET_ON_P1()                    pd_internal_cfet_on(0, false)


/* Function/Macro to turn consumer FET for P1 OFF. */


* Disbale Buck Boost converter, turn off Consumer FETs, set direction to provider mode

* and turn off PWM I which limits current consumption.


#define APP_VBUS_SNK_FET_OFF_P1()                   pd_internal_cfet_off(0, false)


2. @ file power_bank.c

line#49: comment out #define VBATT_MON_GPIO                         (GPIO_PORT_2_PIN_1)


line#64 - line#94 : Comment out all of contents in function void pb_typec_set_current (uint16_t cur_10mA)


line#151 -line#165: Comment out all of contents in function static uint16_t pb_get_battery_voltage(void) to fake battery voltage check (Return a constant value with 4.2V to let power bank state machine tuning well.)


3. @ file power_bank.h

line#51 - line#59 Comment out all of MACRO defines for PWM control.




There are two dongle reference design based on CCG3:

Type-C plug to DisplayPort:

Type-C plug to HDMI/VGA/DVI:

Charge-Through Dongle (equal to Type-C plug to USB3.0/HDMI/Type-C (charge only)) :


If you are going to merge a single Type-C port (Receptacle) into your USB3.0/DisplayPort/HDMI input device. The Type-C plug is not nice to show up on your products. This blog is recommended to take a look.


Below content is schematic explain Type-C receptacle DRP Reference Design (Power source & DisplayPort Sink and USB 2.0 host role <Need wire DP/DM to USB2.0 host.>).

1. Block Diagram:

2. In Details:

a. Part number can suit for this design (Since USB bootloader firmware project is not applied to all of CCG3 device, this design cannot apply to all of devices of CCG3 to save bootloader customize efforts.):

b. PS8742B can be replace with others same function DE MUX (Support DisplayPort Sink at least). CCG3 support I2C/PWM/GPIO control. This design use I2C control (CCG3 is I2C master).


c. DP_Indicator is used for inform DisplayPort/HDMI sink control system that DP ALT Mode is entered and DisplayPort signals is coming.


d. USB2.0 Switch wire to CCG3 internal billboard by default. If attached USB2.0 Device and sink on Type-C receptacle, USB2.0 switch will switch to USB2.0 host in the system.

Cypress SDK firmware demonstrate below feature in difference SDK firmware (@ December, 2018).

1. CCGx Host SDK (…  )

>> Power Source and Sink Role;

>> DisplayPort Source Role with Alternate Mode.


2. CCGx Power SDK (… )

>> Power Source and Sink Role;


3. CCGx Dock SDK (  )

>> Power Source and Sink Role;

>> DisplayPort Sink Role with Alternate Mode.


If you want to change DisplayPort Role based on above #1 and #3, either DisplayPort Source to DisplayPort Sink or DisplayPort Sink to DisplayPort Source. Only need take attention on below define to make sure below defines have been configured as per design requirements.


For Example: DisplayPort Source based Projects change to DisplayPort Sink.

@file: config.h


/* Enable Alternate Mode support when CCG is DFP. */

#define DFP_ALT_MODE_SUPP                           (0u)



/* Enable DisplayPort Source support as DFP. */

#define DP_DFP_SUPP                                 (0u)



/* Enable Alternate mode support as UFP. */

#define UFP_ALT_MODE_SUPP                           (1u)



/* Enable DP Alternate mode support in UFP mode. */

#define DP_UFP_SUPP                                 (1u)


@file: alt_modes_config.h


#define DFP_MAX_SVID_SUPP                       (0u)



#define UFP_MAX_SVID_SUPP                       (1u)


#define MAX_SVID_SUPP                           (DFP_MAX_SVID_SUPP > UFP_MAX_SVID_SUPP ? \

                                                        DFP_MAX_SVID_SUPP : UFP_MAX_SVID_SUPP)


@Software: EZ-PD configuration Utility

a. Open Ez-PD configuration Utilities to add SVID of DisplayPort Sink.

b. Select SVID Configuration and click +Add, SVID 0 will be add under SVID Configuration.

c. Select SVID 0 and edit SVID value and Mode on the right page. Change SVID value 0x0000 (default) to 0xFF01, Mode 0 value from 0x0 to 0x00001405(Plug design)/0x00040045(receptacle design).

d. Click File>Save As.

e. Find the .c file under the folder you have been saved on step c) above.

f. Open config.c under Source files in project. Change config table const unsigned char __attribute__ ((section (".configSection"), used)) gl_config_table[0x0400] by replace the table value from the .c file from Ez-PD configure Utilities above.


Otherwise, DisplayPort Sink change to DisplayPort Source is revise above ENABLE and DISABLE items.

1. New created CCGx project based on example code. (Use CCGx Host SDK, since the CCGx project in the Host SDK have includes i2c-boot project.)

  • File >> New >> Project…
  • Select project type >> Target kit: EZ-PD CCGx HOST SDK (CCG3)

  • Select project template >> Code example


  • Select a code example >> CYPD3125-40LQXI_notebook


  • Create Project>> name workspace/specify location/name project name.

  • Add i2c_boot project into workspace: right click “Workspace”, select Add>> Existing Project…


2. Boot-loader Project Changes.

  • Open TopDesign.cysch of i2-boot project. And then double click Bootloader_1 component to Make sure that the “Dual-application bootloader” option is unchecked.

  • Open config.h file from i2c-boot project head files. Enable define CCG_DUALAPP_DISABLE (CCG_DUALAPP_DISABLE is set as 0u for dual images by default.)

  • Compile the project to generate the customized single bootloader binary (.hex & .elf).


3. Application Project Changes (notebook example).

  • Pre-build CYPD3125-40LQXI_notebook. cyprj project and generate all relates files.
  • Open the CYPD3125-40LQXI_notebook. cyprj project using PSoC Creator 4.2 (the latest version). Double click Bootloadable_1 component and updates the. hex file and .elf file from above process.

  • Update Project -> Build Settings -> Debug -> Debug Target from Application Code and Data 2 to Application Code and Data.

  • Update linker script for single image build.

  • Open the “Project -> Build Settings -> ARM GCC -> User Commands” section and add the following pre-build command.

cmd /c "copy .\Bootloader\CYPD3125-40LQXI_i2c_boot_1_0_3_461_0_0_0_nb.c Generated_Source\PSoC4\cybootloader.c & copy .\Bootloader\CYPD3125-40LQXI_i2c_boot_1_0_3_461_0_0_0_nb.icf Generated_Source\PSoC4\cybootloader.icf"

-----------------------------------------Make sure first step was completed----------------------------------------------

  • Build All project


-- Attach files:

1. Guide.pdf -- steps for Create a single firmware build based on CCGx Host SDK v3.2.1 example project PDF format.

2. -- Example project based on CYPD3125-40LQXI_notebook.

3. cm0gcc.ld -- link script for single image.

Below errors may be met if you are using the new CCG5 example project under CCGx HOST SDK (…  ).


1. Forgot to pre-build backup_fw.

>> After click File >> New >>Project Projectmenu option also allows you to create a new project based on existing example projects. Please kindly Add backup_fw from the project folder you have been pointed to when you new created a project with PSoC Creator.

2. Meet one ERROR caused by PSoC Creator 4.2 (C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin) is not be added into system environment path.  ('cyelftool.exe' is not recognized as an internal command, operable program or batch file.)

3. Meet one ERROR caused by post_build.bat Project name is not changed as per new project name if NEW project name is not CYPD5225-96BZXI_notebook or CYPD5125-40LQXI_notebook. (CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf: Failed to open CortexM0\ARM_GCC_541\Debug\CYPD5225-96BZXI_notebook.elf)

>> Kindly OPEN post_build.bat and edit it


CCG3 DRP Porting from CTD US

Posted by LisaZ_26 Moderator Aug 23, 2018

This Blog documents how to port DRP USB3.0 and DisplayPort 4 lane and remove CTD US functions from Charge Through Dongle (CTD) upstream project. Original example project can be get it from CCGx SDK V3.0.2. LINK:… 


1. Disable I2C Master +HPI INT. The original code (CTD) uses I2C Master interface for HPI with CTD DS.

2. Disable USB-I2C master bridge mode support @file config.h.

/* Enable USB-I2C master bridge mode support. */

#define APP_I2CM_BRIDGE_ENABLE                      (0u) //CTD clear 1->0


3. Comment out all of function related CTD DS. I used Marco define DISABLE_CTD_US and add it into file config.h.

@file main.c

Comment out all of functions which is named begin with "ctd_". And register Application callback functions for the DPM without "ctd_".

Clear content of function void sln_pd_event_handler(uint8_t port, app_evt_t evt, const void *data)


@file ctd_us_solution.c

Comments all functions. Recommend to add #ifndef DISABLE_CTD_US //Clear CTD after all of #include @ file ctd_us_solution.c.


4. Example project attached with Blog. What's I was customized can be found with "DISABLE_CTD_US".

CCG3 SDK notebook firmware example project is Dual Role Power (Power source and Power sink) and support Data source (DisplayPort source or USB3.x data host). It is regards as hardware of CY4531 board.

a. SDK firmware download link:…

b. CY4531 download link:


CCG3 have Integrated Hardware based over-current protection (OCP), related pin is pin#39 OC Over-current Sensor Input. The standard circuits recommended to realize OCP can be refer below (highlight with red box).


You are correct that this is only on Provider path. Which meant the firmware is following the hardware design, the OCP only on Power source role. If you are designing a power sink with CCG3 and could like to implement OCP on consumer path. This is the right place to take a look.


Copy functions with power source role and update OCP features in sink role. (The OCP on power source role is disabled, since this is UFP target.)

Hardware end, you need Rsense 10mOhm on power consumer path same as above. (Change the Rsense from power Provider path to power Sink path).  


Firmware end, you can re-use the function which is using in VBUS_OCP on power source role. Below example functions your may need to be refer to.

a. Add Function declarations for OCP at file psink.c.


static void psnk_dis_ocp(uint8_t port);

static void psnk_shutdown(uint8_t port, bool discharge_dis);

void app_psnk_vbus_ocp_cbk(uint8_t port);


b. Add Type-C current level as per Type-C SPEC.


/* Type-C current levels in 10mA units. */

#define CUR_LEVEL_3A    300

#define CUR_LEVEL_1_5A  150

#define CUR_LEVEL_DEF   90


static const uint32_t cc_rp_to_cur_map[] = {






c. Update psnk_enable function. Example as below with VBUS_OCP_ENABLE


void psnk_enable (uint8_t port)


    uint8_t intr_state;



    uint32_t ocp_cur;


    const dpm_status_t *dpm_stat = dpm_get_info(port);

    intr_state = CyEnterCriticalSection();


    if (dpm_get_info(port)->dpm_enabled)



            if (get_pd_port_config(port)->protect_en & CFG_TABLE_OCP_EN_MASK)


                if (dpm_stat->pd_connected)


                    ocp_cur = dpm_stat->snk_cur_level;




                    ocp_cur = cc_rp_to_cur_map[dpm_stat->snk_cur_level];



system_vbus_ocp_en(port, ocp_cur, app_psnk_vbus_ocp_cbk);


    #endif /* VBUS_OCP_ENABLE */       






d. Add a new function for power sink ocp call back.



void app_psnk_vbus_ocp_cbk(uint8_t port)


    /* OCP fault. */

    /* Quickly turning off fets here, although dpm_stop will also do that. */

    psnk_shutdown(port, true);

    /* Stopping dpm before sending app event. If OCP retry logic is enabled, app will

     * restart the dpm. */


    /* Enqueue HPI OVP fault event. */

    app_event_handler(port, APP_EVT_VBUS_OCP_FAULT, NULL);



#endif /* VBUS_OCP_ENABLE */


e. Add a new function for power sink OCP disable.


static void psnk_dis_ocp(uint8_t port)



    if (get_pd_port_config(port)->protect_en & CFG_TABLE_OCP_EN_MASK)




#endif /* VBUS_OCP_ENABLE */



f. Add disable OCP when power sink is shut down. Example as below with VBUS_OCP_ENABLE



static void psnk_shutdown(uint8_t port, bool discharge_dis)


    /*Turn Off Source FET*/



    if(discharge_dis == true)





    /* Disable OVP/OCP */

app_ovp_disable (port, false);



#endif /* VBUS_OCP_ENABLE */






CCGx footprint for layout.

Posted by LisaZ_26 Moderator Jun 4, 2018

This is place to share CCGx footprint for Cadence. (continue to update regarding CCGx update)

1. CCG1 (35-WLCSP, 40-QFN, 16-SOIC)

2. CCG2 (20_CSP, 14-DFN, 24-QFN)

3. CCG4 (40-QFN, 24-QFN)

4. CCG3 (40-QFN,42-CSP, 32-QFN)

5. CCG3PA (24-QFN, 16-SOIC)

6. CCG5 (96_BGA, 40_QFN)


Each package will update only once, the same package can apply same footprint for difference part number.

1. [CCG2 is power sink role] Adjust request PDO as per SOURCE CAP advertised.


{CCG2 firmware is following PD 2.0 SPEC, the function static bool is_src_acceptable_snk(tPD_DO* pdo_src, tPD_DO* pdo_snk) @ file cy_solution.c is for checking which sink PDO is acceptable based on the SOURC_CAP from DFP. CCG2 firmware is select out the one match the SOURCE_CAP as per Power Delivery SPEC, which is means, the sink voltage and current shall be covered by SOURCE_CAP (Voltage shall be match, Current of SOUCE CAP s larger or equal sink capabilities), otherwise, CCG2 will request 5V request.}

>> Need update the case PDO_FIXED_SUPPLY. Example is below


                    if(fix_volt == pdo_snk->fixed_snk.voltage)


                        max_type_cur = get_max_cur(0u, pdo_snk, fix_volt);

                        if(pdo_src->fixed_src.max_current >= max_type_cur)


                            contract_power = udiv_round_up(fix_volt * pdo_snk->fixed_snk.op_current, 500u);

                            contract_voltage = fix_volt;

                            op_cur_power = pdo_snk->fixed_snk.op_current;

                            out = true;


                        //Added for update current for mismatch current only

                        else if(fix_volt > V_SAFE_5V)


                            contract_power = udiv_round_up(fix_volt * pdo_src->fixed_src.max_current, 500u);

                            contract_voltage = fix_volt;

                            op_cur_power = pdo_src->fixed_src.max_current;

                            max_type_cur = pdo_src->fixed_src.max_current;

                            out = true;





2. [CCG2 is power sink role] Request DR_SWAP or PR_SWAP


{Type-C SPEC defines Power source role as data host by default and power sink role as data device. Type-C can support Power role is not sync with data role. For example, Power source role and data sink role.}

>> Firmware implement process is: (PR_SWAP for example, and expect to work as Power source role.)

a. Check current role.((get_current_port_role() == PRT_ROLE_SINK) )

{There may need add more conditions to go ahead to next step, for example, make sure power source is already asserted.}

b. send PR_SWAP if the current role is not match the expect. (handle_pd_command (DPM_CMD_PR_SWAP, NULL, NULL); )



This is mini customize firmware based on Notebook firmware example for power bank solution. This is Dual Role Port design with software disable and delete DisplayPort, HPI, and I2C master from the project. (Since HPI have pre-build as a library, the HPI cannot disable it totally).


The firmware modification process is almost as below.

  1. Firmware compiler setting before re-build firmware project.

     a. Install MDK.exe from link:

     b. Open CYPD2122-24LQXI project and select Tools>Options>Project Management>ARM Toolchains

     c. Fill ARMCC.exe folder path in ARM MDK Generic (default): (Refer below Figure).



2. Customize source code of Notebook example on Creator

  1. Open/New Create a Notebook project with code example.
  2. Double click TopDesign.cysch and disable HPD, HPI, I2C related components.


And then save all.

     c. Open usbpd_config.h under notebook project Header Files and change below configuration define.


     Open usbpd.h under notebook project Header Files and change below configuration define.



     d. Open file dp_source.c to add below function in it.

void dp_source_init(void)





void dp_source_deinit(void)





tDP_STATE get_dp_state (void)


    return 0;



bool update_dp_config(uint8_t config_cmd)


    return 1;




     e. Set Project”Notebook” as Active, and then rebuild the project. You shall get 26 Errors or more errors as below. And check all errors related MUX (CY4521 hardware have PS874x on board) to clean errors from I2C Master.


     f. Save all changes and re-build project.


-----------------------------------------a clean project can be used for CCG2 DRP (or power bank) design----------------------------------------------