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Version: ** Translation - Japanese: 3.3VでのCY2CC910の最悪立上りおよび立下り時間 – KBA82630 - Community Translated (JA) Question: What are the Worst Case Rise(Tr) and Fall times(Tf) of CY2CC910 at 3.3-V VDD? ... Community Translated by keni_4440091 Version: ** Translation - English: Worst Case Rise and Fall Times of CY2CC910 at 3.3 V - KBA82630 質問： 3.3V VDDでCY2CC910の最悪ケース立上り（Tr）およ... Version: ** Translation - Japanese: 入力リファレンスの削除におけるCY2305の振る舞い - KBA82621 - Community Translated (JA) Question: What is the effect on the CY2305 output when the input reference clock is removed? ... Community Translated by keni_4440091 Version: ** Translation - English: CY2305 Behavior on Removal of Input Reference - KBA82621 質問： 入力リファレンスクロックを削除した場合、CY2305出力の影響はどうなりますか？ &... Translation - Japanese: CY29947の最大ジャンクション温度（Tj）およびジャンクション-周囲間の熱抵抗 - Community Translated (JA) Question: What is the maximum junction temperature (Tj) and thermal resistantance (Theta JA) for the CY29947? ... Community Translated by keni_4440091 Version: ** Translation - English: Maximum junction temperature (Tj) and junction-to-ambient t... Version: *B Translation - Japanese: CY2305のゲートとトランジスタ - KBA86887 - Community Translated (JA) Question: How many transistors and gates does the CY2305SXC-1HT part have? Answer: Cypress̵... Community Translated by YaNi_3193241 Version: *B Translation - English: Gate and Transistors of CY2305 – KBA86887 質問: CY2305SXC-1HTパーツにはいくつの... Author: PradiptaB_11 Version: ** Translation - Japanese: VCXOが有効な場合におけるCY29430 / CY5107の位相ノイズの改善– KBA229132- Community Translated (JA) Phas... Community Translated by NoTa_4591161 Version: ** Translation - English: Improve the Phase Noise for CY29430/CY5107 when VCXO Is Enabled – KBA229132 ... Question: What all RoboClocks are 3.3V-compatible? Answer: The Low Voltage RoboClock (CY7B991V) and RoboClock (CY7B9911V) are completely 3.3V-compatible. The original RoboClock CY7B991/2 (along with the CY7B9... Question: Can I give Spread Spectrum Clock (SSC) input to any Cypress Clock device? Answer: No, this is not true for Cypress clock devices which have on chip PLL. When SSC is given as input to Non-Zero Delay B... Question: Are there any power-up conditions that cause the part to misbehave for 5V RoboClock? Answer: Yes, there are. It is mentioned in Note 3 of the CY7B991/2, CY7B9911 datasheets; and Note 11 of the CY7... Question: I need to set the FS781 filter values to give 0.3%, 0.5% and 0.7% spread bandwidth. They are running at 32MHz. What would the capacitor values be? Answer: In general the FS781 PLL design does not su... Question: When operating the CY23EP05 or CY23EP09 at 2.5V, can I drive it with a 3.3V input clock? Answer: The datasheet specifies a maximum input voltage, VIH, of VDD + 0.3V. This specification reflect... Question: Can the edge rate of the CY23EP05 meet 1.5V/ns when the frequency is 66 MHz and CL=30pf? Answer: The CY23EP05 cannot deliver a slew rate of 1.5V/ns at the 30pF load. The spec for rise/fall time @ 30... Question: The exposed paddle of the CY2DP1510 has no electrical connection. Can it be left floating? Answer: The exposed paddle of the CY2DP1510 must be soldered to the ground plane for heat dissipation purpos... Question: Is there any Trise and Tfall (slew rate) requirement for the input of the Xtal input (Xin) of CY23FS04? Is the input pin (Xin) 5V tolerant? Answer: The XIN and XOUT are crystal input pins for CY23FS0... Question: What is the period and cycle to cycle jitter when banks A and B are at 25MHz and bank C at 50MHz? Answer: The following jitter measurements have banks A and B at 25 MHz, bank C at 50 MHz. ... Question: What is the technology, die size, transistor and gate count for CY2302? Answer: For the CY2302: It's a 0.5 micron technology. The die size is 79x71 mil. And there are 2056 gates.
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