• 書き込みサイクル中の非同期アドレスのグリッチについて - Community Translated (JA)

    Community Translated by KaKi_1384211         Version: **   Translation - English: Asynchronous Address Glitch During Write Cycle     【質問】 書き込みサイクル中のアドレス変更は許容されますか?...
    SivaK_96
    last modified by SivaK_96
  • Understanding of VOH and VOL of QDR (QDR, QDR-II/II+ & QDR-II+ Xtreme) SRAMs - KBA82773

    Version: *B   Translation - Japanese: QDR(QDR, QDR-II/II+ & QDR-II+ Xtreme) SRAMのVOHおよびVOLの理解 – KBA82773 - Community Translated (JA)   Question: Why do the VOH and VOL of QDR SRAMs (QDR, QDR-I...
    SivaK_96
    last modified by SivaK_96
  • UL94V-0_compliance

    Translation - Japanese: UL94V-0準拠について。 - Community Translated (JA)   Question: Are all of your devices UL94V-0 compliant?   Answer: Yes, most of our devices are compliant. However please check with the...
    MohammedA_41
    last modified by MohammedA_41
  • UL94V-0準拠について。 - Community Translated (JA)

    Community Translated by KaKi_1384211   Translation - English: UL94V-0_compliance   【質問】 全てのデバイスはUL94V-0に準拠していますか?   【回答】 はい、ほとんどのデバイスはUL94V-0に準拠しています。 但し、正確な情報につきましては、該当製品の品質レポートを確認してください。
    MohammedA_41
    last modified by MohammedA_41
  • Unused OE# and CE1 Pins

    Translation - Japanese: 未使用時のOE#、及び CE1ピンの処置について。 - Community Translated (JA)   Question: If I am not going to use these pins, what should I do with them?   Answer: If you are not using OE# or CE1, the...
    MohammedA_41
    last modified by MohammedA_41
  • 未使用時のOE#、及び CE1ピンの処置について。 - Community Translated (JA)

    Community Translated by KaKi_1384211   Translation - English: Unused OE# and CE1 Pins   【質問】 OE#、及び CE1ピンを使用しない場合、どのように処置すれば良いですか?   【回答】 OE#、及び CE1を使用しない場合、OE#をGNDに、CE1をVCCへ接続する必要があります。
    MohammedA_41
    last modified by MohammedA_41
  • Reference Schematic Design and Layout Guidelines for Cypress’s Standard Sync/NoBL SRAMs - KBA203263

    Version: **   Translation - Japanese: サイプレスの標準Sync / NoBL SRAMのリファレンス回路図設計およびレイアウトガイドライン - KBA203263 - Community Translated (JA)   Question: Where can I get the reference schematic design and layout gui...
    GeethaP_31
    last modified by GeethaP_31
  • サイプレスの標準Sync / NoBL SRAMのリファレンス回路図設計およびレイアウトガイドライン - KBA203263 - Community Translated (JA)

    Community Translated by YaNi_3193241          Version: **   Translation - English: Reference Schematic Design and Layout Guidelines for Cypress’s Standard Sync/NoBL ...
    GeethaP_31
    last modified by GeethaP_31
  • Termination of Input Pins in Sync SRAMs – KBA82779

    Version: *A   Translation - Japanese: 同期SRAMの入力ピンの終端処理 – KBA82779- Community Translated (JA)   Question: Do all the input pins need pull-up resistors for termination in Sync SRAMs?   Answer: ...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • 同期SRAMの入力ピンの終端処理 – KBA82779- Community Translated (JA)

    Community Translated by YoTa_1693656          Version: **   Translation - English: Termination of Input Pins in Sync SRAMs – KBA82779   質問: 同期SRAMの全ての入力端子...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • シングルビットエラー検出及び訂正のためのError Correcting Codeについて –  KBA90941- Community Translated (JA)

    Community Translated by YoTa_1693656           Version: **   Translation - English: Error Correcting Code to Detect and Correct Single-Bit Errors – KBA90941 &#...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • Back to Back Write in Synchronous SRAMs - KBA82781

    Version: *A   Translation - English: https://community.cypress.com/docs/DOC-20425   Question: Can /WE be kept LOW during back-to-back write operations or does it have to be toggle on every write operati...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • 同期SRAMのライトバック動作について - KBA82781- Community Translated (JA)

    Community Translated by YoTa_1693656          Version: **   Translation - English: Back to Back Write in Synchronous SRAMs - KBA82781   質問: 同期SRAMの/WE信号について、ライト...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • I/O Switching Power for Sync SRAM - KBA82208

    Version: *A   Translation - Japanese: https://community.cypress.com/docs/DOC-20408   Question: Is the IDD (VDD operating supply current) current specified in the sync SRAM datasheets sum of both the core...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • 同期SRAMのI/Oスイッチング電力について - KBA82208- Community Translated (JA)

    Community Translated by YoTa_1693656        Version: **   Translation - English: I/O Switching Power for Sync SRAM - KBA82208   質問: 同期SRAMのデータシートに記載しているIDD(VDDの動作電流)は、コア電...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • 同期NoBL SRAMのADV/LD#ピンの静的レベルとの接続について - KBA83097- Community Translated (JA)

    Community Translated by YoTa_1693656         Version: **   Translation - English: Connecting the ADV/LD# Pin in Synchronous NoBL SRAMs to a Static Level - KBA83097  ...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • Connecting the ADV/LD# Pin in Synchronous NoBL SRAMs to a Static Level - KBA83097

    Version: *A   Translation - Japanese: 同期NoBL SRAMのADV/LD#ピンの静的レベルとの接続について - KBA83097- Community Translated (JA)   Question: Can I connect the ADV/LD# pin in synchronous NoBL SRAMs to a static level? Sho...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • Dummy Read Cycle – KBA89262

    Version: **   Translation - Japanese: ダミーリードサイクルについて – KBA89262 - Community Translated (JA)   Question: What is the significance of the dummy read cycle in SynC SRAMs?   Answer: A dummy read...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • ダミーリードサイクルについて – KBA89262 - Community Translated (JA)

    Community Translated by YoTa_1693656         Version: **   Translation - English: Dummy Read Cycle – KBA89262   質問: 同期SRAMにてダミーリードサイクルの重要性を教えて下さい。   回答: バ...
    ChaitanyaV_61
    last modified by ChaitanyaV_61
  • Nature of Clock Phase Jitter in DDR/QDR™ Sync SRAM – KBA89153

    Version: **   Translation - Japanese: DDR/QDR™同期SRAMのクロック位相ジッターの性質 - KBA89153 - Community Translated (JA)   Question: What type of jitter is specified by tKC Var (clock phase jitter) in DDR/QDR͐...
    GeethaP_31
    last modified by GeethaP_31