Thought I'd introduce the Serial Communication Blocks (SCBs) in the PSoC 6 architecture. Our first PSoC 6 lineup, the PSoC 63 Connectivity lineup has nine SCBs. Each SCB can be configured for either I2C, SPI, or UART. The mode of operation of the SCB can be changed during run time. The PSoC 6 SCBs have two 128 byte deep FIFOs, one for transmit and one for receive. These FIFOs can be written/read by both the CPU and DMA. One of the SCBs out of the nine in PSoC 6 is designed to wake the device up from deep-sleep modes of operation, this SCB is called the deep-sleep SCB. This wakeup can occur on I2C address match, or SPI slave select assertion.
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