Hi everyone!

 

Thought I'd give an update on the PSoC 6 Inter-Processor Communication (IPC) feature for the dual-core ARM Cortex architecture.

The PSoC 6 is a multi-core architecture with two processors CM0+ and CM4 on the same die, with all the memory and peripherals available for use by both the cores. This adds a lot of value to the user who wants to set up a system where the processing load is shared by the two cores. To make such a design possible the two cores must communicate with each other. There are different ways that can happen.

 

At the instruction-set level, you can use the send event instruction (SEV). This generates an interrupt event for each core in a multi-core system. Using the SEV gives you one channel of communication with another core, through the event signal. This means all communication would need to be through this one event. You need to set up a higher layer of code to deal with data transfer and multiplexing of different events.

 

PSoC 6 hardware implements a more capable solution. In addition to the SEV instruction, PSoC 6 has 16 hardware Inter-Processor Communication (IPC) channels. Each channel can be configured to be an exclusive communication medium between the two cores. Each IPC channel implements a hardware semaphore or mutex. You can use this to ensure exclusive access to shared resources. Each channel also has an associated 32-bit shared data register. You can use the register to pass a 32-bit value, or use it for a pointer to any data of arbitrary complexity.

 

In addition to the 16 IPC channels, PSoC 6 also provides 16 IPC interrupts. Each IPC interrupt can be used as event triggers from one core to another. This mechanism can be used in conjunction with an IPC channel to set up a messaging scheme with a notification event and acknowledgement.

 

The Peripheral Drive Library (PDL) implements an API to give you high-level access to the IPC hardware. The PDL implements a semaphore system which can be used to ensure exclusive access to shared resources or single bit flag communication between the two cores. The PDL uses a single IPC channel, but gives you the ability to set up an arbitrary number of semaphores on that channel (limited by available SRAM).

 

In addition, the PDL also provides communication pipe implementations for messaging between cores. Each processor has at least one “end point” structure. Messages are transferred between endpoints. The end point (among other things) has an array of “clients”. Each client has a client ID (the index into the client array and an associated callback function. ”. The messages sent to a specific endpoint can be addressed to a specific client at the end point. Thus each client can be handled differently when a message is sent to it. 

 

Feel free to leave comments and questions, we appreciate the feedback!