Thought I’d give a quick overview of the General Purpose Input Output (GPIO) pins available on PSoC 6. In general they share the high level of configuration and routing flexibility found in PSoC 4 MCUs. The key features are:
Several 8-pin ports include Smart_IO logic, which can be used to perform Boolean operations on signals going to, and coming from pins. Can avoid off chip logic and allow device to enter low power modes by offloading CPU processing.
Eight drive strength modes
Analog input mode (input and output buffers disabled)
Digital Input only
Weak pull-up with strong pull-down
Strong pull-up with weak pull-down
Open drain with strong pull-down
Open drain with strong pull-up
Strong pull-up with strong pull-down
Weak pull-up with weak pull-down
Hold mode for latching current pin state state in Hibernate mode minimizing system power requirements.
Selectable slew rates for dV/dt-related noise control to improve EMI and assist with regulatory compliance testing.
A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex up to 32 analog and digital signals that connect to each I/O pin. Route options include routing peripheral signals to multiple pins and routing Digital System Interconnect (DSI) signals to almost any pin. Routing flexibility simplifies PCB board layout and greatly reduces effort spent allocating pin resources.
Every I/O pin can generate an interrupt if enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it. Improved pin interrupt functionality and register access makes pin ISR configuration and interaction easy.
Standard GPIO pins are rated up to 3.3V.
Four GPIO pins are capable of overvoltage tolerant (OVT) operation where the input voltage may be higher than VDD. These may be used for use cases like I2C to allow powering the chip off while maintaining physical connection to an operating I2C bus without affecting its functionality.