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PSoC 6 MCU

23 Posts authored by: MichiyukiY_91

Hi everyone!

 

Thought I'd give an update on the PSoC 6 Inter-Processor Communication (IPC) feature for the dual-core ARM Cortex architecture.

The PSoC 6 is a multi-core architecture with two processors CM0+ and CM4 on the same die, with all the memory and peripherals available for use by both the cores. This adds a lot of value to the user who wants to set up a system where the processing load is shared by the two cores. To make such a design possible the two cores must communicate with each other. There are different ways that can happen.

 

At the instruction-set level, you can use the send event instruction (SEV). This generates an interrupt event for each core in a multi-core system. Using the SEV gives you one channel of communication with another core, through the event signal. This means all communication would need to be through this one event. You need to set up a higher layer of code to deal with data transfer and multiplexing of different events.

 

PSoC 6 hardware implements a more capable solution. In addition to the SEV instruction, PSoC 6 has 16 hardware Inter-Processor Communication (IPC) channels. Each channel can be configured to be an exclusive communication medium between the two cores. Each IPC channel implements a hardware semaphore or mutex. You can use this to ensure exclusive access to shared resources. Each channel also has an associated 32-bit shared data register. You can use the register to pass a 32-bit value, or use it for a pointer to any data of arbitrary complexity.

 

In addition to the 16 IPC channels, PSoC 6 also provides 16 IPC interrupts. Each IPC interrupt can be used as event triggers from one core to another. This mechanism can be used in conjunction with an IPC channel to set up a messaging scheme with a notification event and acknowledgement.

 

The Peripheral Drive Library (PDL) implements an API to give you high-level access to the IPC hardware. The PDL implements a semaphore system which can be used to ensure exclusive access to shared resources or single bit flag communication between the two cores. The PDL uses a single IPC channel, but gives you the ability to set up an arbitrary number of semaphores on that channel (limited by available SRAM).

 

In addition, the PDL also provides communication pipe implementations for messaging between cores. Each processor has at least one “end point” structure. Messages are transferred between endpoints. The end point (among other things) has an array of “clients”. Each client has a client ID (the index into the client array and an associated callback function. ”. The messages sent to a specific endpoint can be addressed to a specific client at the end point. Thus each client can be handled differently when a message is sent to it. 

 

Feel free to leave comments and questions, we appreciate the feedback!

PSoC 6 Flash

Posted by MichiyukiY_91 Apr 11, 2017

Hello,

 

Thought I'd give an introduction on the flash in the PSoC 6 architecture.

Our first PSoC 6 device has up to 1MB of flash. A flash controller does 128-bit wide flash reads, to reduce power. PSoC 6 flash has read-while-write (RWW) capability, which allows updating the flash while executing from it. This is useful for applications that update flash, such as bootloaders and data loggers. The CPUs in PSoC 6 each have an 8KB 4-way set-associative flash cache. This reduces the number of flash accesses for CPU instructions, which in turn increases CPU execution speed and reduces power. The CPU subsystem architecture incorporates multiple bus masters – the two CPU cores as well as two DMA controllers and a cryptography block (Crypto). Generally, all memory and peripherals are shared by all of the bus masters. Shared resources are accessed through standard ARM multi-layer bus arbitration. Exclusive accesses are supported by an inter-processor communication (IPC) block, which implements hardware semaphores and mutual exclusion (mutexes).

 

Feel free to leave comments and questions, we appreciate the feedback!

PSoC 6 SAR ADC

Posted by MichiyukiY_91 Apr 10, 2017

Hello,

 

Thought I'd give an introduction for the ADC available on the PSoC 6 architecture. The ADC is a Successive Approximation (SAR) type with 12 bits of resolution. It is an updated and improved version of the SAR ADC found on PSoC 4 devices. The key features are:

  • Up to 1 million samples per second at a fixed 12 bits of resolution
  • The programmable analog features of PSoC 6 allow almost every pin to be used as an ADC input. The GPIO pin analog signals can be routed to the ADC through the AMUX busses under software control.
  • A built in 8 channel hardware sequencer can also automatically scan each channel and stores the results for later CPU processing. An upper and lower limit is also able to be compared with each scan and generate an interrupt if an out of range condition is detected.
  • Sequencer channels also support hardware averaging and accumulation of up to 256 samples for lower noise or higher resolution and the resulting 16-bit results.
  • Sequencer allows a software controlled 9th channel to be injected between scans for less frequent measurements. The 9th channel can connect to almost any pin through the AMUX busses. 
  • The ADC provides dedicated connections to the integrated CTBm OpAmps and DAC allowing advanced analog signal effects to be generated and scanned.
  • Supports single ended and differential conversions. The 8 channel sequencer supports up to 4 differential signals.
  • Analog reference is selectable to Vdd, Vdd/2, 1.024V, or an external reference provided to a GPIO pin.
  • Able to read the on chip temperature sensor and supply voltages to allow temperature and voltage based adjustments.
  • Supports one shot or continuous hardware scan triggering and a variety of conversion complete signals that can be used with interrupts, DMA, or custom logic.
  • The ADC control signals and data can be routed to the programmable digital logic (UDBs) to create custom scan functionality, and unique automatic processing of conversion data in hardware.

 

Feel free to leave comments or questions, we appreciate the feedback!

PSoC 6 SysClk

Posted by MichiyukiY_91 Mar 31, 2017

Hello,

 

Thought I'd give an introduction on SysClk in PSoC 6 MCUs. PSoC 6 has an Frequency Locked Loop (FLL) and a Phase Locked Loop (PLL). Both can be used to create High Frequency system clock. For example you can use the FLL to create a clock to run the CM4 and CM0+ cores, while the PLL can be used to clock the audio subsystem. The FLL can achieve an output frequency of up to 100 MHz, while the PLL can reach the device maximum of 150 MHz. The input of the PLL and FLL can be the on board 8 MHz IMO, and external crystal oscillator (ECO), among several other sources.

 

The PSoC 6 device also contains several programmable clock dividers that can be used to clock peripherals such as Serial Communication Blocks (SCBs), Timer/Counter/.PWMs (TCPWMs), and Universal Digital Blocks (UDBs). There are 8 x 8-bit dividers, 16 x 16-bit dividers, 4 x 16-bit fractional dividers with 5 fractional bits, and 1 x 24-bit divider with 5 fractional bits.

 

Feel free to ask questions and leave comments!

Hello,

 

Thought I'd give an introduction to the Bluetooth Low Energy (BLE) peripheral in PSoC 6 BLE MCUs. The PSoC 6 BLE MCU incorporates a Bluetooth Smart subsystem that contains the Physical Layer (PHY) and Link Layer (LL) engines with an embedded security engine. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 2 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth Smart Bluetooth Specification 5.0.

 

Features:

  • 2.4-GHz RF transceiver with 50-Ω antenna drive
  • Digital PHY
  • Link Layer engine supporting master and slave modes
  • Programmable output power: up to 4 dBm
  • RX sensitivity: –95 dBm
  • RSSI: 1-dB resolution
  • 4.2 mA TX (0 dBm) and 4.4 mA RX (2 Mbps) current with 3.3-V battery and internal SIMO Buck converter
  • Link Layer engine supports four connections simultaneously
  • Supports 2 Mbps LE data rate


Happy reading!

PSoC 6 Security

Posted by MichiyukiY_91 Mar 24, 2017

Hello!

 

Thought I'd give an introduction on some of the built-in security features integrated into the PSoC 6 architecture. The PSoC 6 architecture provides hardware-based Trusted Execution Environments (TEEs) with secure data storage, for applications requiring security, such as the many IoT products on the market today. The chain of trust in PSoC 6 starts with internal ROM and user programmable OTP (One Time Programmable) memory. These blocks provide a method to lock down code and settings to make the transition from a normal system to a secure system.  It also offers scalable secure memory for multiple, independent user-defined security policies. In addition, an internal hardware accelerated crypto engine that supports standards such as AES-CMAC, RSA-2048, SHA-256, etc, and dual CPUs (CM0+ and CM4) is also included to speed up the code and data verification process.

 

Happy reading!

PSoC 6 GPIOs

Posted by MichiyukiY_91 Mar 24, 2017

Hello!

 

Thought I’d give a quick overview of the General Purpose Input Output (GPIO) pins available on PSoC 6. In general they share the high level of configuration and routing flexibility found in PSoC 4 MCUs. The key features are:

  • Several 8-pin ports include Smart_IO logic, which can be used to perform Boolean operations on signals going to, and coming from pins. Can avoid off chip logic and allow device to enter low power modes by offloading CPU processing.
  • Eight drive strength modes
    • Analog input mode (input and output buffers disabled)
    • Digital Input only
    • Weak pull-up with strong pull-down
    • Strong pull-up with weak pull-down
    • Open drain with strong pull-down
    • Open drain with strong pull-up
    • Strong pull-up with strong pull-down
    • Weak pull-up with weak pull-down
  • Hold mode for latching current pin state state in Hibernate mode minimizing system power requirements.
  • Selectable slew rates for dV/dt-related noise control to improve EMI and assist with regulatory compliance testing.
  • A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex up to 32 analog and digital signals that connect to each I/O pin. Route options include routing peripheral signals to multiple pins and routing Digital System Interconnect (DSI) signals to almost any pin. Routing flexibility simplifies PCB board layout and greatly reduces effort spent allocating pin resources.
  • Every I/O pin can generate an interrupt if enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it. Improved pin interrupt functionality and register access makes pin ISR configuration and interaction easy.
  • Standard GPIO pins are rated up to 3.3V.
  • Four GPIO pins are capable of overvoltage tolerant (OVT) operation where the input voltage may be higher than VDD. These may be used for use cases like I2C to allow powering the chip off while maintaining physical connection to an operating I2C bus without affecting its functionality.

 

Happy reading!

Interrupts in PSoC 6

Posted by MichiyukiY_91 Mar 20, 2017

Hello out there!

This is an update on PSoC 6 interrupts and its features/capabilities. Feel free to read through and leave a comment!

 

  • PSoC 6 BLE has 139 device interrupt sources from various peripherals such as TCPWM, GPIO, IPC, UDB, SCB, RTC, MCWDT, DMA and many more. These can be connected to either of the two cores - the CM4 which has 240 NVIC lines or the CM0+ which has 32 NVIC lines. Since CM0+ has lesser number of NVIC interrupt lines than the device interrupt sources, a 240:1 multiplexer structure is present on each of the 32 lines to select one of the 139 device interrupt sources.
  • There are 33 interrupt sources that are capable of waking up the core from deepsleep mode. CM4  NVIC lines 0 to 32 and CM0+ NVIC lines 0 to 7 support these deepsleep capable device interrupt sources. 
  • CM4 supports configurable priority from 0 to 7 and CM0+ supports configurable priority from 1 to 3. Priority 0 in CM0+ is reserved for system calls. CM0+ has 32 NVIC lines out of which 4 interrupts are reserved for IPC system calls, IPC Crypto, and IPC pipe interrupts.

 

Happy reading!

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