• About the output CLK_P and CLK_N for CY29411

    Hello   I wrote data in I2C using PSOC in CY29411, but no signal was output from either CLK_P or CLK_N.Please refer to the attachment for details including questions.   Q1) Please tell me why there is no cl...
    NoAr_1540581
    last modified by NoAr_1540581
  • CY2X014LXC100T(EOL) Alternative part CY2942xLXIxxxT

    Have CY294xxLXIxxxT factory-configured part number to replace CY2X014LXC100T? If not, could you provide CY2X014LXC100T factory-configured content for make CY2942xFLXI sample? Or provide CY2942x ClockWirzard project ...
    MiSh_300256
    last modified by MiSh_300256
  • How do I program CY27410FLTXI throu i2c?

    Hello. My project uses the PLL Cypress CY27410FLTXI chip. I want to program it through the I2C interface using the I2C master implemented in FPGA. The configuration data is in the FPGA memory. In order to program it,...
    DmKl_4287586
    last modified by DmKl_4287586
  • CY2907FX8 availability and programmability

    Though CY2907 is obsolete, I a need 5Volt PLL for under a $1 so the CY2907FX8 seems perfect. One (obscure) website shows old new 59392 pcs in stock $0.953 for 100 units.   It will use a crystal input of 14-17MH...
    ToPh_1104671
    last modified by ToPh_1104671
  • Hi.

    Hi. We bought CY22801KFXC chips from DIgi-key But the function is not the same as what we want. We want the chip to behave as I2C slave, And from the data sheet we got to now about the multi-functional pins [3,5,7]...
    sana_4516271
    last modified by sana_4516271
  • Dear sir whether IC  CY22150 can generate the variable pulse width clock or not?

    Dear sir whether IC  CY22150 can generate the variable pulse width clock or not?
    paup_4431351
    last modified by paup_4431351
  • CY294xx at VCXO mode issues

    有一個VCXO Phase Noise 測試問題, 當VC=1/2 VDD時, Phase Noise 測試會有spur產生 而如果避開VC=1/2VDD 就不會. 但是對於VCXO產品, 標準與客戶要求VC=1/2VDD 進行量測基本數據,那麼會有問題的? 請問Cypress 是否有建議的方案, 或後續是否有改善安排? https://www.cypress.com/documentation/applicatio...
    MiSh_300256
    last modified by MiSh_300256
  • CY294xx LVDS 1.8V 40Mhz~100Mhz phase jitter performance

    We had measurement LVDS 1.8V 40Mhz~100Mhz  RMS phase jitter performance about 1.0~1.5ps @12K-20M. But datasheet only show fOUT = 156.25 MHz,12 kHz–20 MHz offset, non-VCXO mode MAX. is 250fs(0.25ps). Could...
    MiSh_300256
    last modified by MiSh_300256
  • What's the difference between CY27EE16ZEC and CY27EE16ZEC-300

    We have both parts in front of us and we do not get the CY27EE16ZEC-300 working.
    NoSt_782071
    last modified by NoSt_782071
  • what's the replacement MPN of CY22150FI

    I saw that,he MPN CY22150FI shows that it is EOL. What is the most suitable replacement MPN? And what is the difference between them
    leka_3804381
    last modified by leka_3804381
  • XP programming only?

    I had to drag out my old XP computer to program a CY22800. NG in 10 or 7. Should we be using this for new designs? Thanks, Rob
    rodec_1012971
    last modified by rodec_1012971
  • Using CY22800 for Audio Clock Generation - Lock Time

    We are currently looking for something to generate an MCLK off of an audio bit clock (ranging from 512 kHz to 3.072 MHz).  This would need to be fixed multiplier of either 4x or 8x.  After a  quick look...
    CoreyW_81
    last modified by CoreyW_81
  • if we activated suspend mode and programmed in CY22393 what will exactly happens?

    I am using cyberclockRT software for programming CY22393. normally S2 and SUSPEND Mode are assigned to the same pin if I activated SUSPEND mode in cyberclockRT software which will deactivate PLL1 completely but if I d...
    PaKu_3818476
    last modified by PaKu_3818476
  • CY29430 Fractional-N Boundary Spurs; "Fout may have [m^Fout-nFref] spurs, choose different reference input clock frequency for better jitter performance-

    I understand the concept of fractional boundary spurs being inherent to fractional-N PLL synthesizer technology; I am not worried about the below warning returned by the ClockWizard software, but I have a few question...
    brcuc_2268776
    last modified by brcuc_2268776
  • Can CY22393FXE (T) output 58kHz?

    Hi,   I have checked the datasheet. I think that CY22393FXE (T) will be able to output 59kHz by PLL and 7-bit divider. Is my understanding correct?   Best regards, Shohei
    ShYa_3490236
    last modified by ShYa_3490236
  • CY29430 LVDS @ Vdd=1.8V; Vocm Output Common Mode Voltage

    Programmable Oscillator CY29430 If I program this oscillator to have LVDS output waveform logic at supply voltage Vdd = 1.8V, it's evident through a few of your application notes and testing that this combination doe...
    brcuc_2268776
    last modified by brcuc_2268776
  • Reprogramming Factory Programmed CY22393/4/5 Device With CY3672

    Is it possible to reprogram factory programmed (pre-programmed) CY22393ZXC-xxx / CY22394ZXC-xxx / CY22395ZXC-xxx devices using the CY3672 with CY3672ADP003A adapter to change the default output frequencies ?   T...
    gudoc_2218941
    last modified by gudoc_2218941
  • CY29421FLXI: Set any clock frequency via I2C

    I need example code how to program the CY29421FLXI to an arbitrary output frequency. This runs in an embedded system without the ClockWizard software for PC. Here's what I have in mind:   void program_CY29421FLX...
    daenc_3574541
    last modified by daenc_3574541
  • please let me know if cypress has alternative parts for 7152A-11 and 7152-01.

    Dear Cypress   Hello. please let me know if cypress has alternative parts for 7152A-11 and 7152-01 of IDT. i would be happy if you attached spec comparison table.   thanks   kimura
    shkic_1534781
    last modified by shkic_1534781
  • PLL configures to program in integer mode by default when fout/fref = rational number. is there a way to DISABLE this function and still program in fractional mode?

    "Fout/Fref appears to be a rational number, PLL configured for Integer-N mode for best jitter performance (FS0)." highlighted below -   Does anyone know if there is a way to disable this default function & s...
    brcuc_2268776
    last modified by brcuc_2268776