• CY7C1470V33-167AXI用fpga控制,通过了仿真模型,上板测试写地址对应的写数据挂在dq上,读数据时所有地址的数据都为最后一个地址的写数据,我将zz拉高拉低不处理情形都一样,我用了32位地址总线,dqpa、dqpb、dqpc、dqpd都用IOBUF进行了处理

    CY7C1470V33-167AXI用fpga控制,通过了仿真模型,上板测试写地址对应的写数据挂在dq上,读数据时所有地址的数据都为最后一个地址的写数据,我将zz拉高拉低不处理情形都一样,我用了32位地址总线,多余的dqpa、dqpb、dqpc、dqpd都用IOBUF进行了处理,我的操作分为读 写 nop三个阶段,nop使用deselect方式进行的控制。原理图如附件所示,请您帮助分析一下是哪里出了问题,多谢。
    last modified by yaya_4678691
  • CY7C1470V33的zz管脚(控制sleep模式)低电平要求多大的电压范围

    我在用FPGA控制zz做sram的写读测试时发现不管zz接1 0或者不接时sram都没有被写进数据,我看datasheet发现测试时zz接的电压小于0.2V,我想请教下是否zz管脚拉低只能在板卡上接地,对于FPGA的LVCMOS33的0输出不能用于控制ZZ管脚
    last modified by yaya_4678691
  • The low voltage standard of zz pin for CY7C1470V33

    Dear engineers of cypress,         I have met some issues when using the  CY7C1470V33.I have past the verilog model test  ,but no data could be  written in  the ...
    last modified by yaya_4678691
  • VHDL model for SRAM CY7C1381KVE33

    Hi all, I need a VHDL model for SRAM CY7C1381KVE33. On Cypress site I have found only the Verilog one. Anyone knows if I may download (or request) an equivalent VHDL model? thanks a lot
    last modified by daba_4679961
  • CY7C4285V-15ASI  PIN 55 GND pin is not connect with the wafer

    part number CY7C4285V-15ASI, the pin 55 for this part is GND part, but it is open, it is not connect with the wafer. would this be an problem to use the part ? will this cause the reliability problem?
    created by AiZh_4671661
  • CY7C1460KV33-200AXC Product Qualification Report

    Hi. Cypress In the web, I can't find out this PN CY7C1460KV33-200AXC Product Qualification Report in website of Device Qualification Reports?would you help to provide it, but others PN can find like cy7c1009d-10vxit ...
    last modified by flfa_1363056
  • CY7C1372D-167AXCについて

    現在、生産中止品になっていますがCY7C1372D-167AXCを使用しています。 型番でCY7C1372D-167AXCKJもあるようなのですが、KJは何を意味しているか分かるでしょうか? RoHS準拠ではないとかでしょうか?
    last modified by user_4634386
  • Tj(max) for QDR II+

    Hello,   Could you provide Tj(max) of QDR II+?   MPN CY7C2265KV18-550BZXI   Best Regards, Naoaki Morimoto
    last modified by NaMo_1534561
  • More detailed power consumption info for radstop QDR devices

    I'm evaluating the CYRS1542AV18 device for my application but the power at max rate is too high. I'd like to evaluate whether at lower clock rates (perhaps even bypassing the DLL) I can bring the power draw low enough...
    last modified by brbu_799096
  • CY7C4141 (QDR-IV) without QKB0 & QKB1 clock output

    CY7C4141 have enabled port A and port B by asserting A[12:11]=11 at reset rising edge (assured by Oscilloscope). But we test the SRAM without QKB0 , QKB1 output all the time , and QKA0,QKA1 are normal. Is that state ...
    last modified by chsi_4622291
  • CY7C1470V33的地址总线和数据总线和PIN脚是如何对应?

    你好!CY7C1470V33的地址总线标记为A,如何把A2~A20分配到对应的PIN脚 ?同理数据总线如何区分? 数据手册中Boundary Scan Order的表格中bit和ball ID表示什么意思?以前用ISSI的SRAM,如下图,数据手册中bit对应的有信号的定义,地址总线A的定义比较清楚,现在用CY7C系列,不知道怎么使用,请解释下,谢谢
    last modified by user_4621486
  • Looking for reliability info (FIT) for the CY62256VNLL-70SNXI

    I can find the reliability documents, but how do I correlate the part I'm looking for to the part families listed in the reports (neither CY62256VNLL-70SNXI nor any reasonable portion thereof shows up in the report do...
    last modified by joha_4606676
  • DFMEA of CY7C1361KVE33-133AXI and CY7C1441KVE33-133AXI

    Hi Cypress   Do you have the DFMEA of this SRAM (CY7C1361KVE33-133AXI and CY7C1441KVE33-133AXI)?Please share this document for us. Thank !!
    last modified by auye_4274126
  • Same broad design of CY7C1526KV18-333BZXC and CY7C1426KV18-300BZXC

    以下の両デバイスをマイグレーション、つまりどちらも実装できるような共通ボード設計方法をご教授頂けますでしょうか。   CY7C1526KV18-333BZXC / 72Mb 8Mbx9bit 333MHz Burst4 CY7C1426KV18-300BZXC / 36Mb 4Mb x 9bit 300MHz Burst4   以上、よろしくお願いいたします。  
    last modified by TaHa_1533676
  • MTBF data of 'CY14B108L/CY14B108N'

    Where can I find MTBF data of 'CY14B108L/CY14B108N' to perform reliability analysis of my board
    last modified by atra_4607156
  • What is CY62128ELL-45ZXI Baking Condition?

    What is CY62128ELL-45ZXI Baking Condition?
    last modified by NaSa_2423976
  • CY7C4142KV13-106FCXC IDDQ current ?

    we want to know what IDDQ current about CY7C4142KV13-106FCXC ? we only saw IDD current in datasheet.thanks  
    last modified by KuLi_1685136
  • Cannot write into CYC1059DV33

    I'm having a problem with CYC1059DV33, probably because this is my first time ever attempt to use any SRAM. It reads as ones, even if I input 0x55 or 0xFF or 0x00. What I noticed via debugging: 1. I set address, fo...
    last modified by SeBo_4571966
  • ODT termination CY7C2665KV18

    Hi, I'm using tha sRAM CY7C2665KV18 and I'm using VDDQ = 1.8 V with Vref = 0.9 V. 1) Is the RQ calculation the same when VDDQ = 1.5 V?   In the "PROGRAMMABLE IMPEDANCE" section, the impedance is RQ*5. In the ...
    last modified by BrId_4495301
  • CY7C2663KV18 sync SRAM

    Hi, I'm using CY7C2663KV18 sync SRAM and there are two pins (BWS0! and BWS1!) that I want connect to GND because I want use all data pins in write-operation. Can I connect those pins to GND or are there problems with ...
    last modified by BrId_4495301