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I need the SARM CY7C2263KV18-550BZXC MTBF, It is better to base on issue4 computing standard. Working on a retro style CPU using mostly HC logic chips for fun. I wanted to try something different with the register file. I could build it too with 8 bit wide logic chips but thought I'd try using a small... We want use NXP MPC5777C MCU to extend Sync. SRAM externally. https://www.nxp.com/files-static/32bit/doc/data_sheet/MPC5777C.pdf But the NXP MPC5777C some pins are ADMUX bus. Cloud you guide us how to implement th... Hi dear friends, I have CY7C2670KV18-550BZI and the marking on the parts is a bit different. There is no country of manufacturing, but I'm not sure it should cause I use https://www.cypress.com/file/41321/d... CY7C1356C - Ok so I am looking at the data sheet, adn I do not see how you set the address. can I mix any of the A's around and get somewhere, my gut is saying no. Most parts have A0 - A15 or something of ... We have multiple Sync. SRAM design on TOP & BOTTOM PCB for save PCB size. Could you have any layout or guideline for reference? Hello I was reviewing the specs for this product and would like to know what the power dissipation is in Watts. I look forward to your response, thank you. Hello It is big honor for me to contact you, as i have small inquire. For CY7C1357C-100BZC, Why itis still in production although it is Leaded SnPb and introduced from 2004? Waiting your reply ... The datasheet for the CY7C25632KV18 shows the maximum current (Idd) for Vdd but does not show the maximum current (Iddq) for Vddq. What is the maximum current draw for the Vddq supply. My current design supplies Vdd a... Hi Cypress Sorry, our layout team has some problem on creating layout pad Could you provide the recommended PCB pad file to us? thank you Although there’s Package Diagrams in the specification, but ... Hello, 我們設計一個使用8顆QDR-II的Memory board。在設計LAYOUT方面參考AN4065 QDR-II Design Guide。但是文件上面沒有提到Data與address的Trace長度需要參考那個部分? Clock signal 是差動訊號嗎? 是否有Layou的設計文件可以參考? 謝謝 Hi Cyperss We looked at the CY62168EV30LL-45BVXI and CY62168G30-45BVXI product specifications on the Cypress website and it looks the same. Can you tell us the difference between CY62168EV30LL-45BVXI and CY621... My questions are regarding the CY7C1381KVE33 (flow through SRAM with ECC, 18Mbits): - What is the failure rate of the CY7C1381KVE33? Please confirm it takes into account the probability for the ECC function to fail. ... CYRS1545AV18 is targeting space applications and the Xilinx Kintex Ultrascale is also marketed for space applications. The CYRS1545AV18 is limited to 250 MHz clock rate. The Xilinx Vivado Ultrascale Memo... 你好，请问Cy有木有可以PIN to PIN替换VTI7512NTMI/512Kbit/TSSOP-8/SPI？这个料是SPI的接口，512Kbit容量，目前来看CY 512Kbit的SRAM只有Async Fast SRAM，PIN to PIN只有NvSRAM和FRAM，这两个价格相对SRAM贵很多，请问Cy的SRAM有木有可以直接PIN to PIN替换VTI7512NTMI/512Kbit/TSSOP-8/SPI？请帮助下... Hello, We are using the obsolete part CY7C1370DV25-200AXC and looking for a functionally equivalent part. We find the CY7C1370KV25-200AXC and want to confirm that we can use it to replace the obsolete part CY7... Dear Sir, We have an application use Xilinx VCU3P platform and need 512MB memory size. We use CY7C4122KV13 at previous project. When we use RDIMM socket & design 8 pcs on the module. How to design choose ... Now Cypress note CY7C1061DV33-10ZSXI is EOL,and recommends we buy CY7C1061G30-10ZSXI,but we don't know the difference between them,I tried to look for the datasheet of both, but it was not very clear The CY7C1441KV33 SSRAM's parasitic input capacitance is specified to be maximum 5pF @ 25°C. I am wondering to which extent this input capacitance can vary with temperature. Many thanks!
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