to follow, share, and participate in this community.
Hi, I try to integrate the verilog model for S27ks0641 with the synopsys SSI IP. I got the following: Warning! Timing violation $skew( negedge CSNe... I'm interested in using an ARM microprocessor with a HyperBus interface attached to an FPGA; where the FPGA is a slave device with memory mapped registers that act as an extension of memory space to the uProc. Does Cy... SudheeshK_26 locked a discussion without actually answering a question. Why is that? Too many cases open to meet their performance goals? Hello, We have designed an FPGA board and now testing it. There are S71KS512SC0BHV00 MCP (HyperRam HyperFlash) and S70KS1281DPBHI02 HyperRam on it. We have successfully run S70KS1281DPBHI02 HyperRam at 150 Mhz... Hello. Does the HyperBUS(flash,RAM) have the tsop, soic or QFP package? Thanks and Best regards. Glenn. Hello, Can we feed Hyperram's CK and CK# diffirential clock buses with SSTL18I io standard? I read that Hyperram's inputs and outputs are LV-CMOS compatible on datasheet. Do we have to use LVCMOS18 io s... I implemented your HyperBus Memory Controller IP on several technology. Now I am trying it on different technology. I have a issue and I want to learn cause of problem. I configured the HyperBus Memory Controller IP a... 希忘有一份 读写yper. Ram和初始化hyper ram的代码或者波形，作为开发的参考，希望各位提供帮助 您好，我确定我的上电初始化是按照数据手册给的时序，我的cs#和reset#都有上拉电阻，具体上电流程是这样的， 上电时序启动拉低reset#超过200ns ，并且cs#一直保持高电平，经过小于150us的时间再拉低cs#并且执行第一次写操作，您感觉我的上电初始化对吗？ 另一个问题想请教一下，关于自刷新我一直是忽略的，没有任何操作，没次进行读写操作的时候都是拉高cs#400ns左右然后开始进入传输C/A的状态，我现在读写数据只进行6... 对于hyper ram的上电初始化有疑问，我怀疑我一直没有驱动起来这个memory，因为从hyper ram 发出的rwds 一直为高电平吧，并且DQ一直是8’h01，希望尽快得到您的帮助 Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to convert to psuedo differential. Has this been tried, is there a recomm... I am looking for Thermal Resistance and Temperature Junciton Max... Thanks! Hi Could you tell me the difference between S27KS0641 and S27KS0642 ? What should be changed when migrating from S27KS0641 to S27KS0642 ? Thanks and regards. Grace I'm requesting the IBIS file for the S70KS1281. Temporarily, a modification of the S27KS0641 can get me by but I hope the S70KS1281 IBIS file will be available soon. I am looking for a future growth plan for the HyperRAM parts. What sizes and when they will be available. The current 128mbit parts do not meet our needs but they would if there was a 256mbit part. Thanks... I see the diagrams and discussions about connecting multiple slave hyperrams to a master. is it possible to do that with the two slaves being in parallel instead of separately accessed? the same controls a... Dear Support team , Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU We have successfully integrated S27KL0641DABH... Hi, I am looking for a Static-RAM kind of device that can meet our performance, space and power requirements. Our requirements are; Random read bandwidth of about 150 MB per sec for burst read size of 1 ... Hello, We have nxp example for access hyperram S27KS0641. But we need to replace the hyperram with multichip S71KS512SC0 (both hyperram and hyperflash). Does the same example can function in both ? I ...
Get a feed of this content