• S27ks0641-$skew error for CSNreg

    Hi, I try to integrate the verilog model for S27ks0641 with the synopsys SSI IP. I got the following: Warning!  Timing violation            $skew( negedge CSNe...
    clab_4481021
    last modified by clab_4481021
  • Using an FPGA as a HyperBus slave

    I'm interested in using an ARM microprocessor with a HyperBus interface attached to an FPGA; where the FPGA is a slave device with memory mapped registers that act as an extension of memory space to the uProc. Does Cy...
    KePa_4518811
    last modified by KePa_4518811
  • Question closed without an answer

    SudheeshK_26 locked a discussion without actually answering a question. Why is that? Too many cases open to meet their performance goals?
    KePa_4518811
    last modified by KePa_4518811
  • HyperRam communication problem in MCP

    Hello,   We have designed an FPGA board and now testing it. There are S71KS512SC0BHV00 MCP (HyperRam HyperFlash) and S70KS1281DPBHI02 HyperRam on it. We have successfully run S70KS1281DPBHI02 HyperRam at 150 Mhz...
    omgu_4560031
    last modified by omgu_4560031
  • Does the HyperBUS(flash,RAM) have the tsop, soic or QFP package?

    Hello.   Does the HyperBUS(flash,RAM) have the tsop, soic or QFP package?   Thanks and Best regards.   Glenn.
    GlJe_1688511
    last modified by GlJe_1688511
  • Hyperram diffirential CK supported IO standart

    Hello,   Can we feed Hyperram's CK and CK#  diffirential clock buses with SSTL18I io standard? I read that Hyperram's inputs and outputs are LV-CMOS compatible on datasheet. Do we have to use LVCMOS18 io s...
    user_4064026
    last modified by user_4064026
  • HyperBus Memory Controller IP does not response write transaction during write response(BVALID remains deasserted)

    I implemented your HyperBus Memory Controller IP on several technology. Now I am trying it on different technology. I have a issue and I want to learn cause of problem. I configured the HyperBus Memory Controller IP a...
    user_4064026
    last modified by user_4064026
  • Hyper ram读写代码

    希忘有一份 读写yper. Ram和初始化hyper ram的代码或者波形,作为开发的参考,希望各位提供帮助
    user_4409276
    last modified by user_4409276
  • Hyper ram 的rwds和dq一直为一个状态

    您好,我确定我的上电初始化是按照数据手册给的时序,我的cs#和reset#都有上拉电阻,具体上电流程是这样的, 上电时序启动拉低reset#超过200ns ,并且cs#一直保持高电平,经过小于150us的时间再拉低cs#并且执行第一次写操作,您感觉我的上电初始化对吗? 另一个问题想请教一下,关于自刷新我一直是忽略的,没有任何操作,没次进行读写操作的时候都是拉高cs#400ns左右然后开始进入传输C/A的状态,我现在读写数据只进行6...
    user_4409276
    last modified by user_4409276
  • 对于hyper ram的上初始化有疑问,我一直没有驱动起来hyper ram,我怀疑是上电初始化的问题,因为从hyper ram发出的rwds信号一直是高电平

    对于hyper ram的上电初始化有疑问,我怀疑我一直没有驱动起来这个memory,因为从hyper  ram 发出的rwds 一直为高电平吧,并且DQ一直是8’h01,希望尽快得到您的帮助
    user_4409276
    last modified by user_4409276
  • Using logic to convert to differential clock?

    Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to convert to psuedo differential. Has this been tried, is there a recomm...
    BeCr_3107286
    last modified by BeCr_3107286
  • KS0641 ibis

    Hi
    GrWa_2302706
    last modified by GrWa_2302706
  • S70KS1281DPBHI023 - Thermal Resistance and Tj

    I am looking for Thermal Resistance and Temperature Junciton Max...   Thanks!
    Sade_4357781
    last modified by Sade_4357781
  • Difference between S27KS0641 and S27KS0642

    Hi   Could you tell me the difference between S27KS0641 and S27KS0642 ? What should be changed when migrating from S27KS0641 to S27KS0642 ?   Thanks and regards. Grace
    GrWa_2302706
    last modified by GrWa_2302706
  • S70KS1281 IBIS File

    I'm requesting the IBIS file for the S70KS1281. Temporarily, a modification of the S27KS0641 can get me by but I hope the S70KS1281 IBIS file will be available soon.
    toduc_677646
    last modified by toduc_677646
  • Is there plans to expand HyperRAM beyond 128mbit?

    I am looking for a future growth plan for the HyperRAM parts.  What sizes and when they will be available.  The current 128mbit parts do not meet our needs but they would if there was a 256mbit part. Thanks...
    jobr_4199181
    last modified by jobr_4199181
  • can hyperram be connected in parallel to make the data accesses 16 bit instead of just 8

    I see the diagrams and discussions about connecting multiple slave hyperrams to a master.  is it possible to do that with the two slaves being in parallel instead of separately accessed?  the same controls a...
    jobr_4199181
    last modified by jobr_4199181
  • grbage data read from Hyperam

    Dear Support team ,   Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU     We have successfully integrated S27KL0641DABH...
    gapac_3691236
    last modified by gapac_3691236
  • HyperRAM Random Read performance

    Hi,    I am looking for a Static-RAM kind of device that can meet our performance, space and power requirements. Our requirements are; Random read bandwidth of about 150 MB per sec for burst read size of 1 ...
    dhve_3751301
    last modified by dhve_3751301
  • S27KS0641 and S71KS512SC0

    Hello,   We have nxp example for access hyperram S27KS0641. But we need to replace the hyperram with multichip S71KS512SC0 (both hyperram and hyperflash).   Does the same example can function in both ? I ...
    rashc_3721956
    last modified by rashc_3721956