• 请问S26F512S hyperflash的擦写相关问题

    您好!客户主mcu是 S6J328C,用S26F512S 做图形存储,在做主mcu的bootloader,更新fyperflash图片信息升级代码过程中,这个时候测试突然通讯终端或者突然掉电,导致擦写flash失败。然后客户会遇到系统重新上电或者重新连接到通讯后,flash擦写函数会异常,擦函数也擦不掉,写入也写入不了。当前用的是我们的低级库驱动函数,正常可以擦写。但是中断后会有这个问题,初步怀疑hyperflash内部逻辑不对,...
    wagu_1442321
    last modified by wagu_1442321
  • 45nm vs 65nm? Differences?

    Can we reuse driver for S26KL512SDABHV020 which uses 65 nm MirrorBit Process Technology for S26HL01GTFPBHB020 which uses 45-nm MirrorBit Process Technology?
    romi_4094216
    last modified by romi_4094216
  • How to connect HyperFlash with HyperRam in layout

    I want to use both - HyperRam ( S70KS1281DPBHI020 128Mb) and HyperFlash (S26KS512SDPBHI020 512Mb) on the same HyperBus (using 2 different CSn lines).   Do you have any layout example?   I don't use Multi-...
    MaMe_3156226
    last modified by MaMe_3156226
  • Need ibis model for hyperMCP "s71ks512sc0bhv000"?

    Hi,   I'm using HyperMCP part s71ks512sc0bhv000 in one of our applications. Since we want to run simulations to evaluate signal quality, need ibis mode for s71ks512sc0bhv000.   Can anybody please provide...
    srpi_4619666
    last modified by srpi_4619666
  • S26KL256S memory mapped mode, read craches after address jump

    I use the hyperflash S26KL256S with STM32L4R9 processor. It works fine sofar for erasing, program etc.. But in memory mapped mode for read, it crashes if i read w aord at address a1 and immediately read the word at ...
    GaZh_4623356
    last modified by GaZh_4623356
  • How to erase a specific sector for S26KL series

    I am using S26KL256S with STM32L4+ processor. I am new in using that IC. How can i erase a specific sector say sector number 17 (starting sector is zero), bit 47 = 0, bit 46 indicate register space and then?   ...
    GaZh_4623356
    last modified by GaZh_4623356
  • Hyperbus control register read write

    Hi,   We are integrating microblaze (from xilinx) with hyperbus IP. And we are using AXI4.   We tried to write control registers like MCR0, GPOR, Loopback registers of HyperBus IP. But all the register val...
    vij_4605301
    last modified by vij_4605301
  • i can not erase the S26KS512

    I can not erase the s26Ks512 , after the erase operation, i got the status register code 0xA2. that mean the chip is locked,but  the ppb and dyb code both were 0xffff.
    jasu_4600241
    last modified by jasu_4600241
  • Recommended stencil thickness for S26KL256SDABHB023(VAA024)

    Hi team,   Could you please let me know the recommended stncil thickness for S26KL256SDABHB023(VAA024)?   Thanks and regards, Katsu.Kikuma
    KaKi_1384211
    last modified by KaKi_1384211
  • S28HS512TGABHM010 lower level driver and ref. demo board software document

    Hi. Cypress   customer use S28HS512TGABHM010 to design , they hope we may provide lower level driver like the web seach file:"https://www.cypress.com/search/all/Low%20Level%20Driver%20for ", I can't find this PN...
    flfa_1363056
    last modified by flfa_1363056
  • Electrical issues s27KS0641

    Hello ,   I am currently trying to integrate the HyperRam memory and noticed that the signal level from the device is low (less than 1 V). The picture below shows an example of the waveform coming out of the d...
    JoAd_4137206
    last modified by JoAd_4137206
  • about unused INT# and RSTO# pins of HyperFlash

    Hello   Q1. Should unused INT# and RSTO# pins of HyperFlash be opened?   Q2. Which document clearly describes about an answer to Q1?   Regards,   Koji
    KoYa_1937921
    last modified by KoYa_1937921
  • HyperRAM user refresh

    The HyperRAM data sheet says :     The host system may also effectively increase the tCMS value by explicitly taking responsibility for performing all refresh and doing burst refresh reading ...
    j.m.granville_2505236
    last modified by j.m.granville_2505236
  • S26KS512S - Drivers Libraries

    Hi all,   are there example driver Libraries available for S26KS512S in context of Linux? We are using the Hyperflash together with an SoC solution from TI (Jacinto).   Thank you in advance Michael
    mimuc_2792966
    last modified by mimuc_2792966
  • EXPOSED PAD in FM24CL64B-DG

    In data sheet you registering "The EXPOSED PAD should not be soldered on the PCB."     Why did you choose packing with EXPOSED PAD?     If I do not solder the EXPOSED PAD still will by ...
    userc_39813
    last modified by userc_39813
  • What processors support hyperflash / hyperbus?

    I see that the iMX.RT supports Hyperlash?  What other processors support Hyperflash / Hyperbus?
    MiRo_263836
    last modified by MiRo_263836
  • Is there any layout or design guide line for S71KL512SC0BHV000?

    Is there any layout or design guide line for S71KL512SC0BHV000? Can't find any guide line information from CYPRESS website for this part number.
    LeSu_449306
    last modified by LeSu_449306
  • Clock connection to FPGA

    Hey, I would like to use your HyperBus memory. My board will contain cyclone V too. My question is, how the clock pin in the HyperBus should be connected? To a standard IO of the FPGA or to a dedicated CLK  p...
    פלגכצנלסון
    last modified by פלגכצנלסון
  • 在FPGA上通过串口烧写S25FL128S / Write S25FL128S through the serial port in FPGA

    你好,我们需要通过串口烧写挂在FPGA上的S25FL128S,FPGA为Xilinx公司的A7系列。串口程序已有,想问一下有没有烧写的IP或者逻辑程序?我找到有在Altrea的FPGA上烧写的文档  https://www.cypress.com/file/202476/download   ,在Xilinx上有没有类似的呢?谢谢~~ Hi, we need to write the S25FL12...
    zhzh_4187791
    last modified by zhzh_4187791
  • Axi-lite or axi hyperbus memory controller IP

    Hi, I have read the HyperBus Memory Controller IP specification (HyperBus_Ctrl_IP_Spec_v2p40) and I have an important doubt. In this document are mentioned AXI and AXI_LITE as interfaces for Control registers (Figure ...
    user_4045201
    last modified by user_4045201