• CY7C1059DV33 visual inspection

    這顆本體右上腳有一個圓形沒有在规格定义里,请帮忙确认
    user_87129
    last modified by user_87129
  • CY7C0853V-133BBI

    Does anyone here have the .bsdl file for this device? I'm trying to "JTag" this device.   Jtag is not working for me. What am I missing here...
    brandon_4278271
    last modified by brandon_4278271
  • CY62148EV30LL-45ZSXI Bit inversion

    Hi,   I think that the cause of SRAM's data bit inversion is soft error and power supply noise. Are there any other factors that cause bit inversion? If you know other possible factors, please provide us. ...
    MaMi_1205306
    last modified by MaMi_1205306
  • CY14B101LA-BA45XIのBGA IBISファイル

    CY14B101LA-BA45XIのIBISが必要です。   CY14B101LA - IBIS https://www.cypress.com/documentation/models/cy14b101la-ibis?source=search&keywords=CY14B101LA&cat=software_tools   上記からダウンロードできるIBISファイルはBGAタイプのSR...
    tatsumi-j_2823561
    last modified by tatsumi-j_2823561
  • CY62148G30-45ZSXI ECC function

    Hi,   CY62148G30 has an ECC function.   Furthermore, This device has not ERR terminal.   What happens if multi-bit error occurs?   However, the data sheet has the following description. --Data...
    MaMi_1205306
    last modified by MaMi_1205306
  • SRAM address pins

    Hello Cypress Team,   We are planning to use your SRAM as alternate to our current SRAM in our board product. But our current part has Address 17 (A17) at pin 30 and Address 18 (A18) at pin 1 from which on your ...
    Gilbert.Decena_4261626
    last modified by Gilbert.Decena_4261626
  • About PIN183401 CY62157EV30

    We have a question about PIN183401. When we see the DC characterization, power consumption is increasing. Also, junction temperature is changed. Please clarify why these characterization are revised before and after ...
    furusawa-s_1540346
    last modified by furusawa-s_1540346
  • Where is data sheet for CY62155

    Where can I find a data sheet for CY62155 that includes CY62155E-3XWI? If not the full data sheet at a minimum, what does the last "5" denote? The seventh character in the Async SRAM appears to be Bus Width. From t...
    GrCa_1363456
    last modified by GrCa_1363456
  • CY62157EV30LL-45ZSXI Data write and read related

    Hi, we have developed your prototype board using LPC4088 and CY62157EV30LL-45ZSXI. In our project we are using LCD for display process data. LPC4088 having internal LCD controller hence we have mapped frame buffer ...
    raviraj.banswal_1424276
    last modified by raviraj.banswal_1424276
  • CY62147EV30LL-45ZSXI about NC pin

    We have a question about CY62147EV30LL-45ZSXI.   On datasheet, SRAM 28 pin is NC and it says that we cannot connect to NC pin.   1) To what does NC pin connect inside of the SRAM? 2)  If we connect a...
    furusawa-s_1540346
    last modified by furusawa-s_1540346
  • CY62146GE30-45BVXI & CY62147GE30-45BVXI WhichRecommend

    Which do you recommend for CY62146GE30-45BVXI & CY62147GE30-45BVXI? I think that CY62146 has better tDBE specs. What is the merit of CY62147?
    yamakoshi.to_1469256
    last modified by yamakoshi.to_1469256
  • Is there any Tj (junction temperature) data available for the CY7C024?

    The datasheet references ambient temperatures, both operating range and absolute maximum, but there seems to be no junction temperature information included. Specifically, is there an operating range maximum for junct...
    eric.williams4_4075631
    last modified by eric.williams4_4075631
  • Hello Community Members

    I am looking for a direct drop-in replacement for CY62146VLL-70ZI. Seeing that this SRAM chip has gone obsolete, I was looking at the CY62146EV30 MoBL chip. Unfortunately, the EV30 has a different pin-out than the CY6...
    frank.flemingsii_4060801
    last modified by frank.flemingsii_4060801
  • CY62157EV30LL-45BVXIのインターポーザについて

    CY62157EV30LL-45BVXI(VFBGA48)のインターポーザランドの開口径を教えて頂けますか?
    nakamura_h_2218186
    last modified by nakamura_h_2218186
  • CY7C1021DV33-10ZSXI  - Write cycle query

    Hello, We are using 1Mb ASYNC SRAM  CY7C1021DV33-10ZSXI in our new design. The datasheet of this device mentioned 3 modes of write cycle on page - 9 and 10. These modes are - 1) Write Cycle No. 1 (CE Contro...
    tarnag.jindal_2283911
    last modified by tarnag.jindal_2283911
  • About read cycle of CE and OE of SRAM CY7C1061G/GE

    Hello,   Customer refer to the SRAM read control by "Figure 15. Read Cycle No. 3" in the datasheet on page 12. In this access, is it possible to read data correctly from SRAM even when "OE goes to Low before CE...
    NaMo_1534561
    last modified by NaMo_1534561
  • PCB design considerations for CY7C1069G30-10ZSXI

    We are using four of CY7C1069G30-10ZSXI in parallel to get a 32-bit data bus connected to a FPGA as host. - Is it any need for length matching in the pcb layout when using these SRAM's? - Are there any PCB design gu...
    losj_3845501
    last modified by losj_3845501
  • CY62157EV30LL SRAM initialization issue

    Hi, We are using LPC4088 based custom board interfacing external nor-flash(SST39vf3201), SRAM(CY62157EV30LL) & FPGA on static memory CS3, CS1, CS0 respectively. We are using Nor-flash for code storage & execu...
  • What is the length matching requirements for the Address, Data and control group of Async SRAM

    Hello, We are using Async SRAM "CY7C1021DV33-10ZSXI" from cypress. As per datasheet and other design guideline document from cypress, there is no length matching requirements listed. but as it is a parallel bus, we...
    tarnag.jindal_2283911
    last modified by tarnag.jindal_2283911
  • 5V compliant I2C SOIC8 FRAM devices

    Can I ask whether there are plans to build 5V compliant I2C SOIC8 FRAM devices with a greater capacity than 8k bytes please ?
    swmcl_3869071
    last modified by swmcl_3869071