• デュアルポートRAM非同期型と同期型の比較 - Community Translated (JA)

    Community Translated by  MoTa_728816          Version : **   質問: - 非同期型と同期型デュアルポートRAMの主な違いについて教えてください。 - どちらかを使用する場合の利点と欠点を教えてください。 - どのような状況下で非同期/同期の選択をした方が良...
    PraveenM_86
    last modified by PraveenM_86
  • FIFO Empty と Full フラグの発生について  - Community Translated (JA)

    Community Translated by  MoTa_728816          Version : *A   質問:Cypress FIFO メモリにおいて FIFO Empty と Full フラグはどのように発生されますか?   回答:FIFO は 2つのポートを有しています。一方は書込み用...
    PraveenM_86
    last modified by PraveenM_86
  • Flow-through versus Pipelined memory – KBA221475

    Version: **   Question: - What is the difference between flow-through (FT) and pipelined (PL) modes? Which mode should I use? Why are newer dual-ports pipelined only?   Answer: Flow-through dual-port mod...
    chaitanyav_41
    last modified by chaitanyav_41
  • Generation of FIFO Empty and Full Flags - KBA85082

    Version: *A   Question: How are FIFO empty and full flags generated in Cypress FIFO memories?   Answer: A FIFO has two ports - one dedicated to writing and one to reading. Each port is addressed by its ow...
    userc_44961
    last modified by userc_44961
  • General-Purpose Memory Controller (GPMC) Configuration for Interfacing the TI Processor (AM335x) with Dual-Port Memories – KBA91141

    Version: **   Question: What is the GPMC configuration for interfacing the TI processor (AM335x) with Dual-Port memories?   Answer: The TI processor (AM335x) has GPMC configuration registers. Based on the p...
    userc_45255
    last modified by userc_45255
  • Clock Ratio Specifications for High-Density FIFO (HDFIFO) - KBA88198

    Version: **   Question: What are the Clock Ratio specifications for HDFIFO?   Answer: As specified in the device datasheet, both read (RCLK) and write (WCLK) clocks should be free-running. Also, the WCLK-to...
    karthiks_
    last modified by karthiks_
  • Simultaneous access arbitration in asynchronous dual-ports

    Question: - What happens if I try to access the same memory location from both ports at the same time?- If I read from one port and write from another at the same time, what data will be read out?- What happens if I w...
    userc_44961
    last modified by userc_44961
  • Replacing obsolete asynchronous dual-port RAMs

    Question: The part I was using is now obsolete. What is a good replacement part?Is there something I can use to replace this asynchronous dual-port?What is important when picking a replacement asynchronous dual-port? ...
    userc_44961
    last modified by userc_44961
  • Chip Disable Issue on CY7C131E/131AE/136E/136AE Dual Port SRAM – KBA86919

    Version: **   Answer: Question: Cypress had the following Chip Disable issue with the CY7C131E/131AE/136E/136AE Dual Port Static RAM: The Chip Enable (CE) pin did not tristate I/Os of the Dual Port RAM under ...
    userc_45255
    created by userc_45255
  • Depth Expansion of CY7C42x1 / CY7C42x1V Synchronous FIFOs

    Answer: Questions: - What design considerations are there when depth cascading multiple CY7C4231 FIFOs? - What needs to be done with the flags when depth cascading? Response: Applications often req...
    userc_44961
    last modified by userc_44961
  • CY7C419 / 421 / 425 / 429 / 433 Pin Configuration for SOJ package

    Question: What is the pin configuration of the molded SOJ package   Answer:  Although not specified exactly in the datasheet, the pin configuration for a molded SOJ package for asynchronous FIFO's is the s...
    userc_45200
    last modified by userc_45200
  • /BUSY & /INT signal architectures: Migrating from RAM28 to RAM42 technology

    Question: What is the difference in the IO architecture for /BUSY and /INT signals between the RAM28 and the RAM42 Dual Port SRAMs?   Answer: This KB pertains to the /BUSY and /INT pins implementation on SPCM As...
    userc_45195
    created by userc_45195
  • /BUSY Signal in Dual Port SRAMs

    Question: /BUSY signal functionality in Dual Port SRAMs   Answer: The Asynchronous dual port devices allow simultaneous access of the memory locations. Such simultaneous accesses may lead to memory access colli...
    userc_45195
    created by userc_45195
  • Lead Free (Pb-free) Dual Port/FIFO/Quad Port Part Number Change

    Question: What changes are made to the Lead Free (Pb-free) part numbers for specialty memory (Dual Port/FIFO/Quad Port) products?   Answer: Response: To obtain new lead free (Pb-free) part numbers, please add an...
    userc_44961
    last modified by userc_44961
  • Availability of FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466

    Question: Where can we look for information on the following FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466?   Answer: Response: Unfortunately, we do not manufacture the FIFO parts CY7C460, CY7C462, CY7C464 ...
    content.librarian
    last modified by content.librarian
  • MoBL DP - IRR/ODR functionality and their benefits

    Question: What are IRR/ODR, their functionality and benefits?   Answer:   Benefits: Why is it good to have IRR and ODR.   The Input Read Register (IRR) and the Output Drive Register (ODR) are des...
    userc_44961
    last modified by userc_44961
  • Aggregate bandwidth and throughput of synchronous FIFOs

    Question: - How is the aggregate bandwidth of a synchronous FIFO calculated?  - How is the aggregate throughput of a synchronous FIFO calculated?   Answer: Generally the aggregate bandwidth and throug...
    userc_44961
    created by userc_44961
  • Programming the Almost Empty / Almost Full (PAE, PAF) Flags

    Question: - How do I program the PAE and PAF flags?  - What is the valid range for PAE and PAF flags?  - How do I store the PAE and PAF values?   Answer: Programmable flags are provided to allow the d...
    userc_44961
    created by userc_44961
  • Read Pointer operation in CY7C42x1 FIFOs

    Question: - Is the address pointer incremented when REN1 & REN2 are asserted, RCLK is toggled, but OE is not asserted?  - What happens if RCLK is toggled, but only REN1 is asserted (REN2 is not)?   Answe...
    userc_44961
    created by userc_44961
  • Tapped Serial Delay Lines Using FIFOs

    Question: How can you implement a tapped serial delay line using a FIFO?   Answer:  These can be made by clocking both the read and write ports of a single FIFO with the same clock. The key to proper opera...
    userc_44961
    created by userc_44961