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Community Translated by MoTa_728816 Version : ** 質問： - 非同期型と同期型デュアルポートRAMの主な違いについて教えてください。 - どちらかを使用する場合の利点と欠点を教えてください。 - どのような状況下で非同期/同期の選択をした方が良... Community Translated by MoTa_728816 Version : *A 質問：Cypress FIFO メモリにおいて FIFO Empty と Full フラグはどのように発生されますか？ 回答：FIFO は 2つのポートを有しています。一方は書込み用... Version: ** Question: - What is the difference between flow-through (FT) and pipelined (PL) modes? Which mode should I use? Why are newer dual-ports pipelined only? Answer: Flow-through dual-port mod... Version: *A Question: How are FIFO empty and full flags generated in Cypress FIFO memories? Answer: A FIFO has two ports - one dedicated to writing and one to reading. Each port is addressed by its ow... Version: ** Question: What is the GPMC configuration for interfacing the TI processor (AM335x) with Dual-Port memories? Answer: The TI processor (AM335x) has GPMC configuration registers. Based on the p... Version: ** Question: What are the Clock Ratio specifications for HDFIFO? Answer: As specified in the device datasheet, both read (RCLK) and write (WCLK) clocks should be free-running. Also, the WCLK-to... Question: - What happens if I try to access the same memory location from both ports at the same time?- If I read from one port and write from another at the same time, what data will be read out?- What happens if I w... Question: The part I was using is now obsolete. What is a good replacement part?Is there something I can use to replace this asynchronous dual-port?What is important when picking a replacement asynchronous dual-port? ... Version: ** Answer: Question: Cypress had the following Chip Disable issue with the CY7C131E/131AE/136E/136AE Dual Port Static RAM: The Chip Enable (CE) pin did not tristate I/Os of the Dual Port RAM under ... Answer: Questions: - What design considerations are there when depth cascading multiple CY7C4231 FIFOs? - What needs to be done with the flags when depth cascading? Response: Applications often req... Question: What is the pin configuration of the molded SOJ package Answer: Although not specified exactly in the datasheet, the pin configuration for a molded SOJ package for asynchronous FIFO's is the s... Question: What is the difference in the IO architecture for /BUSY and /INT signals between the RAM28 and the RAM42 Dual Port SRAMs? Answer: This KB pertains to the /BUSY and /INT pins implementation on SPCM As... Question: /BUSY signal functionality in Dual Port SRAMs Answer: The Asynchronous dual port devices allow simultaneous access of the memory locations. Such simultaneous accesses may lead to memory access colli... Question: What changes are made to the Lead Free (Pb-free) part numbers for specialty memory (Dual Port/FIFO/Quad Port) products? Answer: Response: To obtain new lead free (Pb-free) part numbers, please add an... Question: Where can we look for information on the following FIFO parts CY7C460, CY7C462, CY7C464 & CY7C466? Answer: Response: Unfortunately, we do not manufacture the FIFO parts CY7C460, CY7C462, CY7C464 ... Question: What are IRR/ODR, their functionality and benefits? Answer: Benefits: Why is it good to have IRR and ODR. The Input Read Register (IRR) and the Output Drive Register (ODR) are des... Question: - How is the aggregate bandwidth of a synchronous FIFO calculated? - How is the aggregate throughput of a synchronous FIFO calculated? Answer: Generally the aggregate bandwidth and throug... Question: - How do I program the PAE and PAF flags? - What is the valid range for PAE and PAF flags? - How do I store the PAE and PAF values? Answer: Programmable flags are provided to allow the d... Question: - Is the address pointer incremented when REN1 & REN2 are asserted, RCLK is toggled, but OE is not asserted? - What happens if RCLK is toggled, but only REN1 is asserted (REN2 is not)? Answe... Question: How can you implement a tapped serial delay line using a FIFO? Answer: These can be made by clocking both the read and write ports of a single FIFO with the same clock. The key to proper opera...
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