to follow, share, and participate in this community.
Community Translated by MoTa_728816 Version : *A 質問： Cortex-M0 と Cortex-M0+ はどこが違うのでしょうか？ 回答： Cortex-M0+ プロセッサは Cortex-M0 プロセッサ を基に開発されたもので... Version: ** Question: What are the manual settings required to generate a clock of 48 MHz and accuracy of +/-0.25% for USB operation using FLL, for PSoC 6 MCU? Answer: Do the following: In the Workspa... Version: ** This article provides details on the firmware deliverables from Cypress in Mbed™ OS. Figure 1 shows the architecture of Mbed OS (Source: Mbed OS Documentation). For a general overview o... Author: DheerajK_81 Version: ** Question: The mbed-os-example-aws-iot-client code example requires the information of AWS parameters to be added to the configurat... Author: LinglingG_46 Version: ** Question: How to wake up PSoC® 6 MCU device from Hibernate mode using free running WDT? Answer: PSoC 6 has multiple watchdogs ̵... Author: GeonaM_26 Version: ** In a BLE GATT server, the profile-related data are structured in a database called the GATT database. The GATT database consists ... Author: DheerajK_81 Version: ** This article addresses issues related to PyOCD encountered when debugging Mbed™ OS applications. PyOCD is... Author: WangS_81 Version: ** The SFlash inside PSoC® 6 MCU occupies a 32-KB flash sector. Data stored in SFlash includes device trim value, Flash... Author: WangS_81 Version: ** The access to the SMIF block can be by two modes: MMIO mode or XIP mode. The MMIO mode lets you use the QSPI block as a p... Author: OleksandrP_61 Version: ** Context: PSoC® Creator™ 4.2 project with the Em_EEPROM Component v2_0, v2_10 or v2_20, for PSoC 3, PSoC 4, PSoC 5LP, ... Author: WangS_81 Version: ** Question: How can I generate a combined hex file merging both app0 and app1 for a basic device firmware update for PSoC... Author: DheerajK_81 Version: ** Question: Why Opamp OA0 output is not available in the pin 9 while OA1 output is working fine with the same Opamp settings? ... Author: SrikanthD_56 Version: *A PSoC 6 MCU on some of the early PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) and PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFiB... Author: vitas_81 Version: ** Question: I am using PSoC® Creator™ 4.2, PDL 3.1.0, and PSoC Programmer 3.28 tools and trying to debug the CM4 core... Author: ShanmathiN_06 Version: ** The SCB_EZI2C_PDL Component can wake up the device from Deep Sleep mode on a Slave address match. To enable this function... Author: LinglingG_46 Version: ** Question: Can I use the PSoC6 BLE Pioneer Kit as a programmer to program external PSoC® devices? Answer:... Author: GeonaM_26 Version: ** Question: How do you set BLE transmit power level over Host Controller Interface (HCI) mode in PSoC® 6 MCU BLE? ... Author: LinglingG_46 Version: ** Question: Is there a power sequence required for different supplies such as VDDD, VBACKUP, VDDIO, and VDDA in PSoC® 6? Answe... Author: SergiiV_71 Version: ** Question: Why fault occurs when Cy_USBFS_Dev_Drv_Disable() is called with USBFS driver endpoint management mode configured to CPU Manual... Author: XZNG Version: *A Question: How can I keep the UART baud rate stable if the peripheral clock (Clk_Peri) is dynamically changed for low power designs in PSoC® 6? &...
Get a feed of this content