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Version: ** Question: How should I implement a USBFS composite device for PSoC® 3, PSoC 4L, or PSoC 5LP? Answer: USB composite devices are the devices that would enumerate as multiple device classes... Version: ** Question: How can I resolve "The flash row is not valid for the selected array" error in the Bootloader Host for PSoC® 3, PSoC 4, or PSoC 5LP bootloader designs? Answer: This error appea... Version: ** Question: How often should I change the data in nonvolatile latches (NVLs) in PSoC 3/5LP? Answer: NVLs in PSoC 3/5LP are used to store important configuration data that will be used to config... Version: ** Question: Can MiniProg3 be used to program PSoC® 1 devices? Answer: Yes, MiniProg3 can be used to program PSoC 1, PSoC 3, or PSoC 5LP devices. It can be used with Bridge Control Panel or... Version: ** Question: How do you dynamically control a GPIO connected to hardware output using firmware in PSoC® 3/5LP? Answer: GPIO output data can be driven from either the data output register or... Version: ** Question: How should the error conditions be correctly handled when UDB UART is used with PSoC 3, PSoC 4, andPSoC 5LP Designs? Answer: The UDB UART supports detection of errors like parity, s... Version: ** Question: Are there any over-current or connection issues with the Miniprog3 *A? Answer: There are known electrical risks to the Miniprog3 *A revision with respect to over-current protection... Version: ** Question: When I try to update a Component in PSoC Creator™ 4.1 I get an error similar to what’s shown below: Error message: “Error: Unable to install parcel ‘... Version: *B Question: What is Cypress Commercial and Government Entity Code or CAGE CODE? Answer: The Commercial and Government Entity Code, or CAGE Code, is a unique identifier assigned to supplie... Question: Whenever I modify the code in component’s generated source file, it gets removed whenever project is built in PSoC Creator. How to make modification to retain after build? Answer: The best wa... Version: ** Question: Where do I determine the Silicon Revision ID for PSoC® 3 devices? Answer: You can find Silicon Revision ID in memory at the address 0x46EC. Follow these steps to view the... Version: ** Question: How do I route the internal reference to an external Pin in PSoC Analog Coprocessor? Answer: The Programmable Voltage Reference Component (PVref) provides a reference voltage... Version: ** Question: How do I program a Cypress device with KitProg2/MiniProg3 by using the LabVIEW software from National Instruments? Answer: LabVIEW supports the ActiveX method to access the C... Version: ** Question: What should I consider if my system is experiencing voltage irregularities? Answer: It depends; some you can ignore, while for some you need to do Power-On Reset (POR) or an ... Version: ** Answer: This document requests an initial check and setup for the CYALKIT-E02 Rev**, because some of Rev. ** kits have different values from the default values listed in the CYALKIT-E02 Kit Guide... Version: ** Question: When using the USB function, can we select the built-in high-speed CR for the master clock? Answer: No. The high-speed CR clock (CLKHC) frequency accuracy does not meet the... Version: *A Question: How do you address individual GPIO pins in PSoC® 3? Answer: Similar to the 8051 code, PSoC 3 offers the flexibility to address the port pins individually. To do ... Version: ** Question: The Dstc_ClearDreqenbBit() function in Peripheral Driver Library (PDL) 2.1.0 sets the DREQENB register bit instead of clearing it. The problem is reproducible on the FM0+ and FM4 family o... Version: ** Question: Selecting analog input channels 8 through 15, and 24 through 31 for ADC conversion is not supported due to a defect in the ADC driver. The problem is reproducible on FM0+ and FM4 family o... Version: ** Question: What are the power modes in which the Programmable Analog Blocks – Universal Analog Block (UAB), Continuous Time Block (CTB), SAR ADC, and Programmable Reference Block (PRB) can be ...
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