• S6BT112A CXPI Transceiver: CLK Pin Output for Slave Node - KBA223645

    Version: **   Question: When using the S6BT112A CXPI Transceiver in Slave node (normal mode), what is the output to the CLK pin?   Answer: The clock on the CXPI communication bus is output to the CLK pin. Th...
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  • Set the S6BT112A CXPI Transceiver to Sleep Mode - KBA223643

    Version: **   Question: How do I set S6BT112A CXPI Transceiver to sleep mode?   Answer: Make the NSLP pin "L" level to make the device enter low-power sleep mode. Change the input to the pin to the "H" level...
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  • S6BT112A CXPI Transceiver: UART Clock and CXPI Communication Bus Clock - KBA223644

    Version: **   Question: When using the CXPI Transceiver in master node, do I need to synchronize the input clock with the UART baud rate?   Answer: No. It is not necessary to synchronize the input clock and ...
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  • Retention of Backup RAM in Traveo™ S6J3110/3120 MCUs - KBA223672

    Version: **   Question: When I set the data to Backup RAM before the MCU transits to the Power Saving State (PSS) mode, the correct data is checked into the memory window of the debugger. But after the MCU return...
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  • Traveo™ S6J3200 MCU: I/O Power Shutdown in PSS Mode - KBA223670

    Version: **   Question: Can the I/O power supply be shut down in the Power-Saving State (PSS) even though I/O control is in the Always-ON power domain 1 (PD1)?   Answer: The wakeup function in the Traveo S6J...
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  • Side Effects of Program Execution Using External Memory in Traveo™ S6J3200 MCU - KBA223673

    Version: **   Question: Is it possible to use HyperFlash™ as a memory extension for code execution for the external HyperBus™ interface of S6J3200?   Answer: Cypress recommends the use of TCM Fla...
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  • Using Chip Select Pin as Port Function in Traveo™ S6J3XXX MCUs - KBA223674

    Version: **   Question: Is it possible to use the chip select pin as a port function when multi-function serial is set to Clock Synchronous Serial Interface (CSIO) mode operation in S6J3110/3120/3200/3300/3350/33...
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  • HyperBus Interface Channel Selection – KBA223297

    Version: **   Question: In the S6J3200 SampleSW hyperbusi example, why is the HyperBus interface ch.0 type (HYPERBUSI0_Type) used for the GPOR register configuration when selecting ch.1? Answer: HyerBus interfac...
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  • TCFlash 64-bit Write Issue in Traveo – KBA223308

    Version: **   Question: Some data bits are incorrect when writing to TCFlash using 64-bit TCFlash Write API (Tcflash_Write64()). How to solve this issue?   Answer: When TCFlash ECC is enabled, 64-bit word wr...
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  • Variation of Parasitic Capacitance (CP) Between Segments in a Slider Design Using Dual IDAC Mode – KBA91404

    Version: *D   Question: How much parasitic capacitance (CP) can vary from one segment to another segment in a slider design using dual IDAC mode?   Answer: A slider has many segments that are separatel...
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  • Emulator Debug Failure of SOFTUNE Workbench - KBA223060

    Version: **   Question: When I select Start debug from the debug menu of SOFTUNE Workbench using MB2100-01A-E Single Port Embedded Emulator Debugger SPEED-BOX, SOFTUNE stops abruptly. How can I prevent the proble...
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  • Port Configuration for PSS Mode in Traveo™ MCUs - KBA222863

    Version: **   Question: Do S6J3110/3120/3200/3300/3350/3360/3370/3400/3510 Traveo series MCUs have any recommended port settings for the lowest power consumption in PSS mode?   Answer: These Traveo series MC...
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  • Behavior of Wakeup from PSS Mode in Traveo™ S6J3110/3120/3200/3300/3350/3360/3370/3400/3510 MCUs - KBA222866

    Version: **   Question: How different is the behavior of these Traveo Series MCUs at wakeup from PSS mode by the setting of the power domain (PD)?   Answer:   When the Peripheral Supply Domain (PD2) 1 ...
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  • PLL0 Clock Down Test of Clock Supervisor in Traveo™ S6J3300/3310/3320/3330/3340/3350/3360/3370/3400/3510 Series MCUs - KBA222351

    Version: **   Question: In the PLL0 clock down test of clock supervisor, CPU is not reset when a CSV error of PLL0 occurs. How can I reset the CPU when a CSV error of PLL0 occurs?   Answer: According to the ...
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  • Exclusive Access Memory in Traveo™ S6J3110/3120/3200/3300/MB9D560 MCUs - KBA222862

    Version: **   Question: What is the usage of exclusive access memory (EAM)?   Answer: This is the memory area where simultaneous access by instructions (STRx, LDRx, STREXx, and LDREXx) from several CPU cores...
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  • Hardware Watchdog during PSS Mode in Traveo™ S6J3110/3120/3200/3300/3310/3320/3330/3340/3350/3360/3370/3400/3510 Series MCUs - KBA222353

    Version: **   Question: Does hardware watchdog stop during power saving state (PSS) mode?   Answer: Yes, the hardware watchdog stops during PSS mode.
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  • Other Flash Sector Write during Sector Erase Suspend in Traveo™ S6J3110/3120/3200/3300/3310/3320/3330/3340/3350/3360/3370/3400/3510 Series MCUs - KBA222352

    Version: **   Question: Is it possible to restart sector erase after writing data to other flash sector during sector erase suspend?   Answer: In TC Flash, it is not possible to write data to other sector du...
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  • Shorten the Secure Boot Time in Traveo™ S6J3110/3120/3200/3300/3310/3320/3330/3340/3350/3360/3370/3400/3510 Series MCUs - KBA222350

    Version: **   Question: How can I shorten the secure boot time?   Answer: If SHE=ON, it is possible to shorten the secure boot time by setting the following registers: Platform manual: BootROM software inte...
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  • Data Retention Voltage of Backup RAM in Traveo™ S6J3200/S6J326C/324C/327C/328C/32DA/32BA/32G0 Series MCU - KBA222235

    Version: **   Question: What is the data retention voltage of Backup RAM?   Answer: LVDL0 is the data retention voltage. See the datasheet for details. S6J3200 Series: Data sheet: http://www.cypress.com/fil...
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  • Clock Source of Multi-Function Serial ch.16 in Traveo™ S6J3300/3310/3320/3330/ 3340/3350 Series MCUs - KBA222269

    Version: **   Question: Which clock source can I supply to the multi-function serial ch.16 that supports I 2C fast-mode?   Answer: It is CLK_COMP, because multi-function serial ch.16 is located in MCU_CONFIG...
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