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Version: ** Question: In the PLL0 clock down test of clock supervisor, CPU is not reset when a CSV error of PLL0 occurs. How can I reset the CPU when a CSV error of PLL0 occurs? Answer: According to the ... Version: ** Question: What is the usage of exclusive access memory (EAM)? Answer: This is the memory area where simultaneous access by instructions (STRx, LDRx, STREXx, and LDREXx) from several CPU cores... Version: ** Question: Does hardware watchdog stop during power saving state (PSS) mode? Answer: Yes, the hardware watchdog stops during PSS mode. Version: ** Question: Is it possible to restart sector erase after writing data to other flash sector during sector erase suspend? Answer: In TC Flash, it is not possible to write data to other sector du... Version: ** Question: How can I shorten the secure boot time? Answer: If SHE=ON, it is possible to shorten the secure boot time by setting the following registers: Platform manual: BootROM software inte... Version: ** Question: What is the data retention voltage of Backup RAM? Answer: LVDL0 is the data retention voltage. See the datasheet for details. S6J3200 Series: Data sheet: http://www.cypress.com/fil... Version: ** Question: Which clock source can I supply to the multi-function serial ch.16 that supports I 2C fast-mode? Answer: It is CLK_COMP, because multi-function serial ch.16 is located in MCU_CONFIG... Version: ** Question: What is the state of the PSC1 pin during a reset? Is pull-down required on this pin? Answer: The PSC1 pin state is not stable if the voltage is below the operation assurance conditi... Version: ** Question: There is a thermal or exposed pad under the TEQFP package of the MB91F59B part. How can I design and connect the exposed pad? Answer: The dimensions of exposed pad for layout design... Version: ** Question: When PLL clock used for a CAN peripheral, how do I verify whether the PLL clock jitter meets the CAN precision specification? Answer: Use the following equation to evaluate the imp... Version: ** Question: Is it possible to check the current output level when the port is set to output? Answer: Yes, you can read the port output level from Port Input Data Register (GPIO_PIDRi) by settin... Version: ** Question: Do the Traveo MCUs have a protection function to prevent program execution for memory area and stack area? Answer: The Traveo MCUs have the memory protection unit (MPU) of Cortex-R5... Version: ** Question: In the 16FX (MB96600 series) C_CAN sample project, CAN messages were not received on some RX channels when MessageObjects larger than 16 were used. How can I solve this issue? ... Version: ** Question: What is the difference in the charging operation of S6AE101A and S6AE102A/103A? Answer: S6AE101A supports a single VSTORE pin to charge a single storage device, which can be a smal... Version: ** Question: The configured LIN-UART baud rate 1.2 kps is not accurate when peripheral clock is 40 MHz. Why and how to get the expected baud rate? Answer: The LIN-UART baud rate is generated fro... Version: ** Question: In Traveo™ MCUs, will an ECC error occur when reading from area 1 with ECC enabled after writing to area 3 in Work Flash memory? Answer: Yes, an ECC error will occur. Version: ** Question: In Work Flash memory, after 64-bit data was written in area 3, is there the method that only writes only the ECC? Answer: There is no method that writes only ECC. Version: ** Question: In case of using only 2D Graphics Engine (without 3D Graphics Engine), is the HyperBus™ performance of S6J327 the same as that of S6J328? Answer: Yes, both MCUs have the same ... Version: ** Question: Can VCC53 driving pins hold I/O signal during PSS mode? Answer: Yes. VCC53 can hold I/O signal during PSS mode. Version: ** Question: Is it possible to use HyperRAM™ for graphic VRAM and Quad Serial Peripheral Interface (QSPI) flash memory for graphic contents data simultaneously? Answer: No, it is not possi...
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