• Differences between CY62147G and CY62146G Asynchronous Memory Parts – KBA219723

    Question: What are the differences between CY62147G/CY62147E/CY62157E /CY62167E and CY62146G/ CY62136F/ CY62146E Asynchronous SRAMs?   Answer: The devices differ from each other in terms of Byte-power down featur...
    chaitanyav_41
    last modified by chaitanyav_41
  • SRAM and DRAM difference

    Question: What is the difference between an SRAM and a DRAM? Does Cypress manufacture DRAM's   Answer: DRAM stands for Dynamic Random Access Memory. It is a type of semiconductor memory in which the memory i...
    MichaelF_56
    last modified by MichaelF_56
  • Difference Between tACE and tDOE – KBA92092

    Version: **   Question: What are the timing parameters of tDOE and tACE for an Asynchronous SRAM? When should you assert /CE and /OE so that you get valid data in tACE and tDOE time during a read operation?  ...
    userc_45255
    last modified by userc_45255
  • Similarities and Differences Between the CY7C199C and CY7C199CN Parts – KBA91346

    Version: **   Question: What are the main similarities and differences between the CY7C199C and CY7C199CN Async Fast SRAMs?   Answer: Both CY7C199C and CY7C199CN are Asynchronous Fast SRAMs based on 0.25 &#...
    userc_45255
    last modified by userc_45255
  • Soft Errors and their Effect on Semiconductor Devices – KBA90938

    Version: **   Question: What is a soft error (SE)? How do SEs affect semiconductor devices? What are the causes of SEs?   Answer: An SE is a random, non-recurring change of state or transient in microelectr...
    userc_45255
    last modified by userc_45255
  • ECC Implementation in Cypress’s 65-nm Asynchronous SRAMs – KBA90940

    Version: **   Question: How is error correcting code (ECC) implemented to mitigate soft errors in Cypress’s 65-nm Asynchronous SRAMs?   Answer: Cypress’s 65-nanometer (65-nm) asynchronous SRAM d...
    userc_45255
    last modified by userc_45255
  • Different Ways to Mitigate Soft Errors in Asynchronous SRAMs – KBA90939

    Version: **   Question: What are the different ways to mitigate soft errors in Asynchronous SRAMs?   Answer: The following methods are commonly used to mitigate soft errors:   Changes in process tech...
    userc_45255
    last modified by userc_45255
  • Error Correcting Code to Detect and Correct Single-Bit Errors – KBA90941

    Version: **   Question: What is error correcting code (ECC)? How does it help in single-bit error detection and correction?   Answer: Error correcting codes are algorithms that allow data that is being read...
    userc_45255
    last modified by userc_45255
  • ISB2 vs Temp and ISB2 vs VCC for CY62147EV30

    Question: Provide the characterization data for ISB2 vs Temp and ISB2 vs VCC   Answer: Characterization data for CY62147EV30 is attached below
    userc_44961
    last modified by userc_44961
  • MoBL SRAM Definition

    Question: What are MoBL SRAMs?   Answer:  MoBL stands for More Battery Life. These SRAM's use up to 90% less power than the standard  low-power SRAM's making them the industry's lowest power consumpti...
    userc_44961
    last modified by userc_44961
  • Floating data input on CMOS SRAM

    Question: I used a SRAM which has a x32 configuration and now I am forced to use a x36 configuration. I have the 4 unused inputs floating. Is this okay?   Answer:  It is not recommended to leave the CMOS i...
    userc_44961
    last modified by userc_44961
  • Erase contents of SRAM

    Question: What is the voltage at which we can ensure the contents of SRAM are completely erased?   Answer:  Data retention voltage could be explained as the lowest possible power supply voltage at which th...
    wenhec_
    created by wenhec_
  • Difference in Maximum and Typical Standby Currents

    Question: Why is there a huge difference between the maximum standby current and the typical standby current.   Answer: The SRAM's are designed to operate with less current in standby mode, however, in extreme ...
    userc_44961
    created by userc_44961
  • Part  Number Decoder for Ultra Low Power SRAMs

    Question: Is a part number decoder for the Ultra Low Power SRAM family available?   Answer: Response: Find attached the part number decoder for the micro  power SRAM  family  . Note that, the deco...
    content.librarian
    last modified by content.librarian
  • Constraints and Interchangeability of Data and Address pins in Async SRAMs

    Question: Can I interchange the address pins in Cypress Async SRAMs ?  Or Can I interchange the data pins in Cypress Async SRAMs ?   Answer:  In Asynchronous SRAMs, the address pins (Ax) can be assign...
  • Byte Power Down feature in MoBL SRAMs

    Question: How does the Byte Power Down feature work in Cypress MoBL SRAMs ?  or If I de-assert both BHE# & BLE#, will my device get deselected ?  or Which devices have Byte Power Down feature available ?...
  • clarify tSCE

    Question: In MPWR SRAMs, when device wakes up from standby, is the time to write solely determined by tSCE?   Answer:  Yes. The minimum /WE pulse required to write the data into a memory cell is called the...
  • Interleaved part

    Question: Is the P/N CY7C1041DV33 an interleaved part? Are the Logical bits physically adjacent in a RAM array?   Answer: The device is an interleaved part. Two adjacent bits of a logical word are separated by ...
    PriyadeepK_01
    created by PriyadeepK_01
  • Load Capacitance of Tri-State Data bus of many SRAMs connected together

    Question: What will be the load capacitance of a Tri-State Data bus when more than one SRAM busses are connected together?   Answer: Eventhough only one SRAM will be using the data bus at a time, it will see th...
    KishoreS_96
    created by KishoreS_96
  • Does CY62256 have pull up resistor on the I/O ?

    Question: Does this part have pull up resistors on the I/O pins?   Answer: Yes, the CY62256 has pmos pull ups on the I/Os. Basically, this specific part is only designed to go up to 3.8V
    userc_44961
    created by userc_44961