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I am confused by the classification of CYBLE-416045 and EZ-Serial Support. Older posts (2019) claim there is no intention for CYBLE-416045 to support...
I am confused by the classification of CYBLE-416045 and EZ-Serial Support. Older posts (2019) claim there is no intention for CYBLE-416045 to support EZ-Serial and I do not see this among listed devices in documentation claiming such support, yet the CYBLE-416045-EVAL I purchased is listed as an EZ-BLE and documentation which comes with the kit references EZ-Serial. Can you please clarify the standing of this module. If there is no intention to make this module support EZ-Serial, what is the closest module to it that does (eg, Bluetooth 5 support, number GPIOs, etc.)
I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM int...
I want to use several 8Mbit x8 SPI 40MHz Excelon LP F-RAM devices in an application where I need to convert signals coming from a parallel x8 SRAM interface to 40MHz SPI signals and also 40MHz SPI signals sourced from the SPI F-RAM device to signals destined for the x8 parallel SRAM interface. As for the x8 parallel SRAM interface timings, conservatively, I have a memory address setup time of around 250ns, a memory address hold time of around 1250ns and a chip enable hold time of around 750ns ( I'm not quite sure of the timings right now and I know I am missing some timing information for some of the x8 parallel SRAM signals ). I plan on doing this with an ultra-low-power MCU, but, I'd need to use cycle-stretching on the Cypress F-RAM device(s). Is the above kind of conversion doable, especially the cycle stretching?
We have implemented a power switch architecture using the CYUSB3304, that is similar to figure 17 of the AN94150 App Note ("Designing a SuperSpeed Hub...
We have implemented a power switch architecture using the CYUSB3304, that is similar to figure 17 of the AN94150 App Note ("Designing a SuperSpeed Hub..."), without the recommended Q1 MOSFET.
In our design we have 4 USB ports and each port has its own USB power switch. The 4 power switches are enabled by a common PWR-EN signal from the CYUSB3304 and the over-current flags out of the power switches are tied together as a common flag back to the CYUSB3304. The 4 power switches receive 5V from a local 5V regulator. The power switches are set to trip at 500mA.
When we create an overcurrent condition, by putting a programmable load on the 5V pin on the USB port, the power switch asserts the OVRCURR pin on the CYUSB3304. In response, the CYUSB3304 switches off the power by de-asserting PWR_EN, which in turn makes the power switch de-assert OVRCURR.
Next, we assume that the CYUSB3304 should periodically check if the overcurrent condition is resolved, by re-asserting PWR_EN and monitoring OVRCURR.
HOWEVER we find that this re-try process takes a very long time and is indeterminate:
When the overcurrent condition is removed, the power enable pin takes a variable amount of time to return to the high state. This time was found to be anywhere between 2 seconds (2 to 5 seconds a few times) and 4.25 minutes (once). Most attempts took 10 to 30 seconds but quite a few were over 1 minute.
In practice, this means that the USB on our product will be disabled for 10-30 seconds after an overcurrent condition - up to 4 minutes.
Is this normal behaviour for the CYUSB3304? If not, what can we do to address this? We would also like a description of the over-current recovery process; the datasheet does not mention it.
The CY6611 USB Hub EVK is now available! Based on the EZ-USB™ HX3PD hub controller (CYUSB4347-BZXC), the CY6611 kit provides a powerful evaluation pl...
The CY6611 USB Hub EVK is now available! Based on the EZ-USB™ HX3PD hub controller (CYUSB4347-BZXC), the CY6611 kit provides a powerful evaluation platform for customers who are interested in building USB docking stations or multi-functional monitors that provide 10 Gbps USB 3.2 Gen 2 ports with USB-C and Power Delivery features.
USB-IF certified USB 3.2 Gen 2 hub silicon (TID # 5030000008).
USB 3.1 Gen 2 (10 Gbps) data transfer on five Downstream (DS) ports (DS1-DS5)
USB 2.0 data transfer on seven DS ports (DS1-DS7)
USB PD 3.0 charging on Upstream (US) and DS1 port
USB Battery Charging (BC v1.2) and other legacy charging standards on four DS ports (DS2-DS5)
The ability to configure and program the HX3PD firmware
Could you please help me with Schematic and firmware design support to drive Segment LEDs using the PSoC 5LP chip?We have to drive a seven-digit s...
Could you please help me with Schematic and firmware design support to drive Segment LEDs using the PSoC 5LP chip? We have to drive a seven-digit seven segment display with various segment current from 16-bit serial input.