I am working on a Flash Write routine which is part of a boot loader for the CY8C27243.  I am using Application AN2100 as a starting point. I have all aspects of the bootloader working except for Flash Write.  After many days of debugging I have narrowed it down to the Supervisor ROM Flash Write sequence which uses the M8C SSC instruction. 

Here is a simplified sequence used to access a supervisor ROM routine as found in FLASHAPI.asm which is part of AN2100. This is part of the temperature table access routine and is a very simple use of the supervisor ROM and should work.

push A   ; save the State variable
push X
mov X, SP   ; copy SP into X
mov A, X     ; mov to A
add A, 3     ; create 3 byte stack frame
mov [0xF9], A   ; save stack frame for supervisory code
mov [0xF8], 0x3A   ; load the supervisory code for flash operations
mov A, 6    ; load A with FLASH_TEMP_TABLE_LOOKUP rom code
SSC          ; SSC call the supervisory code
pop X

Code execution does not return after the SSC instruction. I am assuming it is halting for some reason.

I have double checked all of the parameters and can't figure out what I am doing wrong.  Can SSC only be called when the M8C is in a certain mode ?  I have been able to read Flash successfully since that routine uses the absolute ROM read instruction ROMX which avoids an SCC. I wish there was such an easy way to do a write.

I have been working on this bootloader for nearly a month now and need to finish this before new product release.  

Hi,

I have been working to implement a circuit on PSoC5LP MCU as the PSoC5 LP MCU supports both analog and digital peripherals but in analog we have 4 comparators and 4op-amps, what in the situation if we require MOSFET in the situation, then what should be my approach? 

Anyone Please do let me know, waiting for your reply.

Thanks & Regards,

Prateek

hello,

i've succesfully tried and reproduced the example called "qspi_read_write_using_sfdp".

When i'm importing the rights function in my project, the init function fails (cy_serial_flash_qspi_init).

When i'm digging into the details, it fails when calling Cy_SMIF_MemInit which return CY_SMIF_SFDP_SS0_FAILED

i've compared everything, and i'm not able to find what i'm doing wrong.

is there anybody who experienced the same issue ? thanks

Hello

"AN65974.zip"-> "FX3 Firmware"-> "Slave Fifo Sync"

→ There is the following description on line 892 of "cyfx slfifosync"

io_cfg.gpioSimpleEn [0] = 0;
io_cfg.gpioSimpleEn [1] = 0x08000000; / * GPIO 59 * /
io_cfg.gpioComplexEn [0] = 0;
io_cfg.gpioComplexEn [1] = 0;

Q1)
What will happen to the terminal state when all gpioSimpleEn are set to 0 (disabled)?
Q2-1) I think that the GPIO_SIMPLE register setting described on P.590 of FX3 TRM corresponds to the terminal setting in this case. Is this correct? if so,  would like to know the terminal status and necessary terminal processing in that case.
Q2-2) I think that DRIVE_HI_EN: 0 is a tri-state output if the initial value of the register. Is this correct?
Q2-3) Is it okay if external terminal processing is not required in the case of tri-state?

Please answer each  question mentioned above?

Best Regards

Arai

Hello,

I'm curious to know if it should be possible to send an invalid vendor request code to the Default USB device on an FX2[LP]. I know that the request code 0xa0 is always recognized before and after renumeration. I attempted to send another code that is implemented in our firmware to the default USB device and I expected that it would simply reject the request and stall endpoint 0. In our Windows driver when I attempted to send a URB that packages that vendor request, USBD seems to block indefinitely. After seeing that, I put in logic to cancel the IRP after a timeout elapsed. However, when I went to continue through our usual process of downloading firmware, it seems to malfunction, as if it consumed part of my invalid vendor request and cached it before processing the subsequent 0xa0 vendor request.

Is this just something I should completely avoid doing [sending unrecognized vendor request codes to it]? I managed to move on to a different technique but my motivation was to try to discern between our device having renumerated with firmware and a fresh firmware-less enumeration state. Granted, one can use vendor, product, and device ID combinations to deduce this, but this was something of an academic exercise for me and I'm genuinely curious. I could not find anything in the TRM that would tell me what to expect under this scenario.

~Thanks

Hello Infineon Experts,

We use a CX3 and one or two related image sensors on our board, and we are facing a CY_U3P_ERROR_FAILURE value returned by the CyU3PMipicsiSetSensorControl() API. This behavior is random, but the error rate is over 20 %.

We probed the I2C bus and some other significant signals (CX3_RESET*, CX3_XRESET and CX3_XSHUTDOWN), to look what’s happen (see attached pictures):

• On successful execution, a first reading of Register 0x0012 (CY_U3P_MIPICSI_REG_GPIOIN) is done, bits [2:1] of this value are set to ‘1’ to drive High XRESET and XSHUTDOWN pins, the changed value is written to Register 0x0014 (CX3_CSI_SENSOR_SIG_VAL) and a second reading of Register 0x0012 is performed to be sure that Register 0x0014 is correctly written. So, reserved bits of Register 0x0014 are preserved as requested to section 1.10.7 of CX3 TRM.
• On fail execution, the second reading of register 0x0012 doesn’t match the writing to Register 0x0014 and the CyU3PMipicsiSetSensorControl() API returns CY_U3P_ERROR_FAILURE. The difference concerns the reserved bit 0.

Do you have an explanation for this error CY_U3P_ERROR_FAILURE?

For your information, both SDA and SCL signals are pulled high with 2kΩ resistors, and the I2C block is initialized (by calling CyU3PMipicsiInitializeI2c() API) before initializing the MIPI-CSI-2 block (i.e. before calling CyU3PMipicsiInit() API).

Best Regards,

Eric.

Hello,

I am looking for a cross for Adesto's AT25SF041-SSHD-B.

The absolute size can be larger. However, the SPI serial interface and register set have to be exactly the same.

Thank you!

I need to achieve low standby power consumption in a system with an FX3 and a Xilinx FPGA.  This system primarily remains in a low power idle state for 99% of the time where neither the FX3 or FPGA is being used. 

Referring to the block diagram below, the PSoC is powered continuously through the LDO.  The PSoC controls switching regulators that power a USB host, the FX3 and the Xilinx.  The PSoC also performs aggressive power management to maximize battery life.

The PSoC turns on power to the FX3 and the Xilinx FPGA.  All of the FX3's core VDD(x) and IO VIO(x) supplies are powered.  The FPGA's IO banks connected to the FX3 are powered as well to avoid the FX3 driving an unpowered FPGA or vice versa.

Later, the PSoC will apply power to the USB Host system which in turn powers VBUS on the USB connector.  VBUS is used to hold the FX3 in RESET (using an RC network) until VBUS is stable.

Questions:

1. Will this method of powering the FX3 work? 

2.  I'm confused about the use of VBATT versus VBUS FX3 signals.    The Super Speed Explorer connects VBUS on the USB connector to the FX3's VBUS signal.  The FX3's VBAT signal is not connected on the SSE.   The FX3 DVK connects a select-able power supply(+5V,+3.3,+2.5) voltage or a battery through a diode OR to the FX3's VBAT signal.  VBUS from the USB connector is connected to the FX3's VBUS signal.    Other FX3 based boards connect the VBUS line from the USB connector to both VBAT and VBUS on the FX3.  I'm not sure what is the correct usage for my application.  Please explain.

3. I have other H/S USB devices that would share one USB Gen 3 connector.  It is possible to insert a CY7C65642 USB hub on the D+ and D- signals?

Thanks for your help!

Wayne

3.

Hi everyone,

I'm debugging a camera firmware which is developped based on this: https://www.cypress.com/documentation/application-notes/an75779-how-implement-image-sensor-interface-using-ez-usb-fx3-usb

The cypress camera works fine except that seldomly during video streaming the camera somehow stops and when I check usb desctiption with lsusb -v, I saw that its descriptor is corrupted. And in dmesg I saw:

[ 8720.318320] usb 1-1.4: new high-speed USB device number 28 using xhci-hcd
[ 8720.419525] usb 1-1.4: config 1 contains an unexpected descriptor of type 0x1, skipping
[ 8720.419534] usb 1-1.4: config 1 has an invalid descriptor of length 1, skipping remainder of the config
[ 8720.419540] usb 1-1.4: config 1 has 1 interface, different from the descriptor's value: 2
[ 8720.419548] usb 1-1.4: config 1 interface 0 altsetting 0 has 0 endpoint descriptors, different from the interface descriptor's value: 1
[ 8720.420738] usb 1-1.4: config 1 has an invalid descriptor of length 1, skipping remainder of the config
[ 8720.420747] usb 1-1.4: config 1 has 0 interfaces, different from the descriptor's value: 2
[ 8720.423854] uvcvideo: Found UVC 1.00 device _v1.4.0 (04b4:00f8)
[ 8720.423873] uvcvideo: No valid video chain found.
[ 8720.423919] usb 1-1.4: Unsupported device

 Is there anyone has the same problem ?

Thank you very much